PacketGenerator

Table of Contents Packet generator Project summary Specifications Revision history Download/Installation Install from NetFPGA Yum repository Install from tarball Usage Preparation Stand-alone package NetFPGA source package Packet generation/capture Options Sample output Examples Simple packet replay Packet replay and capture Packet replay with rate limiting Packet replay with zero delay between packets Simultaneous replay and capture on all four ports Packet replay with padding Measuring delay through a switch/router Capture/replay details Timestamping Measurement Capture pcap files Regression Tests Additional Information

Packet generator

This project provides a simple packet generator and capture tool. It is designed for use by anyone who wants to inject packets into a network and/or observe packets exiting a network.

The generation feature in the current implementation is a "playback" mechanism—a sequence of Ethernet frames is loaded from a PCAP dump file into the generator which then proceeds to transmit that sequence of frames. Delay between individual frames can be tightly controlled; by default the generator will use the delay specified in the pcap source file. A user can optionally specify a maximum data rate and/or a set delay between frames.

The packet generator also be used to report statistics on packets exiting the network and optionally to record the packets exiting the network. These feature are useful for analyzing throughput through a device and for analyzing whether the data exiting a network is correct.

Project summary

Status :

Released

Current version :

1.1.1

NetFPGA package requirement :

2.1.1

Authors :

Hardware: Glen Gibb ([email protected]) %BR% Software: Adam Covington, Glen Gibb

Release date :

June 18th, 2010

Specifications

Replay timing accuracy :

Typically within a few hundred microseconds. %BR% The location of the delay module within the pipeline limits the precision because of buffers that follow. This is a known issue and will be addressed at some point in the future.

Capture timestamp precision :

nanoseconds

Capture timestamp accuracy :

nominally ± 8ns (+ any added inaccuracy in the NetFPGA clock) %BR% The NetFPGA's core clock is nominally 125MHz (8ns period). Uncertainty in introduced into the measurement due to a clock-domain crossing. (See the datasheets for the clock part/Virtex II Pro for accuracy of the original clock signal.)

Revision history

See Packet generator revision history for the revision history and to download older versions.

Download/Installation

Install from NetFPGA Yum repository

WARNING: The yum package is not yet available for 1.1.1.

1. Install the NetFPGA Base Package
2. Install the packet generator

 yum install netfpga-packet_generator

Install from tarball

Download from here: http://netfpga.org/releases/netfpga_packet_generator_1_1_1.tar.gz

Usage

Preparation

Stand-alone package

%RED% WARNING: Standalone package not currently available for 1.1.1.%ENDCOLOR% %BR% Run the following command:

 packet_generator_setup.pl

NetFPGA source package

FCCM 2009 Packet Generator Paper