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rniczhrniczh
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add lit test
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‎mlir/test/RTIO/RTIOEventToARTIQ.mlir‎

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// Copyright 2025 Xanadu Quantum Technologies Inc.
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// RUN: quantum-opt %s --convert-rtio-event-to-artiq --split-input-file | FileCheck %s
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// CHECK: llvm.func @now_mu() -> i64
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// CHECK: llvm.func @at_mu(i64)
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// CHECK: llvm.func @rtio_get_counter() -> i64
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// CHECK: llvm.func @rtio_init()
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// CHECK: llvm.func @delay_mu(i64)
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// CHECK: llvm.func internal @__rtio_set_frequency(%arg0: i32, %arg1: f64, %arg2: f64, %arg3: f64)
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// CHECK: llvm.func @rtio_output(i32, i32)
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// CHECK: llvm.func internal @__rtio_config_spi(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32)
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// CHECK: llvm.func internal fastcc @__rtio_sec_to_mu(%arg0: f64) -> i64
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// CHECK-LABEL: func.func @__kernel__()
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// CHECK-SAME: attributes {diff_method = "parameter-shift", qnode}
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module @circuit attributes {rtio.config = #rtio.config<{core_addr = "172.31.9.64", device_db = {core = {arguments = {analyzer_proxy = "core_analyzer", host = "172.31.9.64", ref_period = 1.000000e-09 : f64, satellite_cpu_targets = {"1" = "rv32g"}, target = "cortexa9"}, class = "Core", module = "artiq.coredevice.core", type = "local"}, spi_urukul0 = {arguments = {channel = 17 : i64}, class = "SPIMaster", module = "artiq.coredevice.spi2", type = "local"}, ttl_urukul0_io_update = {arguments = {channel = 18 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, ttl_urukul0_sw0 = {arguments = {channel = 19 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, ttl_urukul0_sw1 = {arguments = {channel = 20 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, ttl_urukul0_sw2 = {arguments = {channel = 21 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, ttl_urukul0_sw3 = {arguments = {channel = 22 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, urukul0_ch0 = {arguments = {chip_select = 4 : i64, cpld_device = "urukul0_cpld", pll_en = 1 : i64, pll_n = 32 : i64, sw_device = "ttl_urukul0_sw0"}, class = "AD9910", module = "artiq.coredevice.ad9910", type = "local"}, urukul0_ch1 = {arguments = {chip_select = 5 : i64, cpld_device = "urukul0_cpld", pll_en = 1 : i64, pll_n = 32 : i64, sw_device = "ttl_urukul0_sw1"}, class = "AD9910", module = "artiq.coredevice.ad9910", type = "local"}, urukul0_ch2 = {arguments = {chip_select = 6 : i64, cpld_device = "urukul0_cpld", pll_en = 1 : i64, pll_n = 32 : i64, sw_device = "ttl_urukul0_sw2"}, class = "AD9910", module = "artiq.coredevice.ad9910", type = "local"}, urukul0_ch3 = {arguments = {chip_select = 7 : i64, cpld_device = "urukul0_cpld", pll_en = 1 : i64, pll_n = 32 : i64, sw_device = "ttl_urukul0_sw3"}, class = "AD9910", module = "artiq.coredevice.ad9910", type = "local"}, urukul0_cpld = {arguments = {clk_div = 0 : i64, clk_sel = 2 : i64, io_update_device = "ttl_urukul0_io_update", refclk = 125000000 : i64, spi_device = "spi_urukul0", sync_device}, class = "CPLD", module = "artiq.coredevice.urukul", type = "local"}}}>} {
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memref.global "private" constant @__qubit_map_0 : memref<2xindex> = dense<[0, 1]>
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func.func @__kernel__() attributes {diff_method = "parameter-shift", qnode} {
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%cst = arith.constant 1.1618250000000001E-6 : f64
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%cst_0 = arith.constant 8.298750e-06 : f64
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%cst_1 = arith.constant 1.6597500000000003E-7 : f64
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%cst_2 = arith.constant 19100000.100724373 : f64
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%cst_3 = arith.constant 20900000.012723904 : f64
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%cst_4 = arith.constant 19000000.026035815 : f64
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%cst_5 = arith.constant 21000000.087412462 : f64
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%cst_6 = arith.constant 19999999.977146666 : f64
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%cst_7 = arith.constant 0.000000e+00 : f64
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// Test rtio.empty, should initialize RTIO and return a timestamp
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// CHECK: llvm.call fastcc tail @rtio_init()
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// CHECK: %[[COUNTER:.*]] = llvm.call fastcc tail @rtio_get_counter()
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// CHECK: %[[OFFSET:.*]] = arith.constant 125000 : i64
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// CHECK: %[[INIT_TIME:.*]] = arith.addi %[[COUNTER]], %[[OFFSET]]
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// CHECK: llvm.call tail @at_mu(%[[INIT_TIME]])
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%0 = rtio.empty : !rtio.event
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// Test rtio.channel, creates channel reference
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%1 = rtio.channel : !rtio.channel<"dds", [2 : i64], 2>
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%3 = rtio.channel : !rtio.channel<"dds", [2 : i64], 0>
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// Test rtio.pulse with wait on empty, should set frequency and generate TTL pulse
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// First pulse on channel 2 waiting on empty event
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// CHECK: llvm.call tail @now_mu()
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// CHECK: llvm.call tail @at_mu
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// CHECK: llvm.call @__rtio_set_frequency
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// CHECK: llvm.call tail @now_mu()
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%2 = rtio.pulse %1 duration(%cst_1) frequency(%cst_6) phase(%cst_7) wait(%0) {offset = 0 : i64} : <"dds", [2 : i64], 2> -> !rtio.event
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// Test parallel pulses, both wait on same event
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// CHECK: llvm.call tail @at_mu
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// CHECK: llvm.call @__rtio_set_frequency
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%4 = rtio.pulse %3 duration(%cst_1) frequency(%cst_6) phase(%cst_7) wait(%0) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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// Test sequential pulse on same channel
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// CHECK: llvm.call tail @at_mu
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// CHECK: llvm.call fastcc tail @__rtio_sec_to_mu
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// CHECK: llvm.call tail @rtio_output
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// CHECK: llvm.call fastcc tail @delay_mu
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// CHECK: llvm.call tail @rtio_output
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%5 = rtio.pulse %3 duration(%cst_1) frequency(%cst_6) phase(%cst_7) wait(%4) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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// Test rtio.sync, synchronizes multiple events using maxsi
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// CHECK: arith.maxsi
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// CHECK: llvm.call tail @at_mu
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%6 = rtio.sync %5, %2 : !rtio.event
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// Test multiple parallel pulses after sync
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%7 = rtio.pulse %3 duration(%cst_0) frequency(%cst_5) phase(%cst_7) wait(%6) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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%8 = rtio.channel : !rtio.channel<"dds", [2 : i64], 1>
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%9 = rtio.pulse %8 duration(%cst_0) frequency(%cst_4) phase(%cst_7) wait(%6) {offset = 1 : i64} : <"dds", [2 : i64], 1> -> !rtio.event
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%10 = rtio.pulse %1 duration(%cst_0) frequency(%cst_3) phase(%cst_7) wait(%6) {offset = 0 : i64} : <"dds", [2 : i64], 2> -> !rtio.event
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%11 = rtio.channel : !rtio.channel<"dds", [2 : i64], 3>
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%12 = rtio.pulse %11 duration(%cst_0) frequency(%cst_2) phase(%cst_7) wait(%6) {offset = 1 : i64} : <"dds", [2 : i64], 3> -> !rtio.event
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// Test sync with 4 events
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// CHECK: arith.maxsi
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// CHECK: arith.maxsi
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// CHECK: arith.maxsi
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// CHECK: llvm.call tail @at_mu
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%13 = rtio.sync %7, %9, %10, %12 : !rtio.event
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// Final pulses after sync
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%14 = rtio.pulse %3 duration(%cst) frequency(%cst_6) phase(%cst_7) wait(%13) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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%15 = rtio.pulse %1 duration(%cst) frequency(%cst_6) phase(%cst_7) wait(%13) {offset = 0 : i64} : <"dds", [2 : i64], 2> -> !rtio.event
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%16 = rtio.pulse %3 duration(%cst) frequency(%cst_6) phase(%cst_7) wait(%14) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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// CHECK: return
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return
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}
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}
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// -----
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// CHECK-LABEL: func.func @__kernel__()
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module @simple_sequential attributes {rtio.config = #rtio.config<{core_addr = "172.31.9.64", device_db = {core = {arguments = {host = "172.31.9.64", ref_period = 1.000000e-09 : f64, target = "cortexa9"}, class = "Core", module = "artiq.coredevice.core", type = "local"}, spi_urukul0 = {arguments = {channel = 17 : i64}, class = "SPIMaster", module = "artiq.coredevice.spi2", type = "local"}, ttl_urukul0_io_update = {arguments = {channel = 18 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, ttl_urukul0_sw0 = {arguments = {channel = 19 : i64}, class = "TTLOut", module = "artiq.coredevice.ttl", type = "local"}, urukul0_ch0 = {arguments = {chip_select = 4 : i64, cpld_device = "urukul0_cpld", pll_en = 1 : i64, pll_n = 32 : i64, sw_device = "ttl_urukul0_sw0"}, class = "AD9910", module = "artiq.coredevice.ad9910", type = "local"}, urukul0_cpld = {arguments = {clk_div = 0 : i64, clk_sel = 2 : i64, io_update_device = "ttl_urukul0_io_update", refclk = 125000000 : i64, spi_device = "spi_urukul0", sync_device}, class = "CPLD", module = "artiq.coredevice.urukul", type = "local"}}}>} {
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memref.global "private" constant @__qubit_map_0 : memref<1xindex> = dense<0>
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func.func @__kernel__() attributes {diff_method = "parameter-shift", qnode} {
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%cst_dur = arith.constant 1.0e-6 : f64
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%cst_freq = arith.constant 20000000.0 : f64
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%cst_phase = arith.constant 0.0 : f64
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// CHECK: llvm.call fastcc tail @rtio_init()
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%0 = rtio.empty : !rtio.event
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%ch0 = rtio.channel : !rtio.channel<"dds", [2 : i64], 0>
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// First pulse, sets frequency and generates TTL
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// CHECK: llvm.call @__rtio_set_frequency
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// CHECK: llvm.call fastcc tail @__rtio_sec_to_mu
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// CHECK: llvm.call tail @rtio_output
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// CHECK: llvm.call fastcc tail @delay_mu
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// CHECK: llvm.call tail @rtio_output
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%1 = rtio.pulse %ch0 duration(%cst_dur) frequency(%cst_freq) phase(%cst_phase) wait(%0) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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// Second pulse, sequential, waits for first
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// CHECK: llvm.call tail @at_mu
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// CHECK: llvm.call fastcc tail @__rtio_sec_to_mu
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// CHECK: llvm.call tail @rtio_output
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// CHECK: llvm.call fastcc tail @delay_mu
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// CHECK: llvm.call tail @rtio_output
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%2 = rtio.pulse %ch0 duration(%cst_dur) frequency(%cst_freq) phase(%cst_phase) wait(%1) {offset = 0 : i64} : <"dds", [2 : i64], 0> -> !rtio.event
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// CHECK: return
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return
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}
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}
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