Skip to content

Commit d8c1b7a

Browse files
committed
improve logic
1 parent 04ee8e2 commit d8c1b7a

File tree

1 file changed

+8
-4
lines changed

1 file changed

+8
-4
lines changed

frontend/catalyst/python_interface/visualization/construct_circuit_dag.py

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -238,12 +238,16 @@ def _flatten_if_op(op: scf.IfOp) -> list[Region]:
238238
has_quantum_ops = False
239239
nested_if_op = None
240240
for op in else_block.ops:
241+
if isinstance(op, scf.IfOp):
242+
nested_if_op = op
243+
# No need to walk this op as this will be
244+
# recursively handled down below
245+
continue
241246
for internal_op in op.walk():
242-
if isinstance(internal_op, scf.IfOp):
243-
nested_if_op = internal_op
244-
break
245-
if "quantum" in internal_op.name:
247+
if type(internal_op) in quantum.Quantum.operations:
246248
has_quantum_ops = True
249+
# No need to check anything else
250+
break
247251

248252
if nested_if_op and not has_quantum_ops:
249253
# Recursively flatten any IfOps found in said block

0 commit comments

Comments
 (0)