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Commit 3bf072d

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firecrafty
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PROS Project Template
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‎.gitignore‎

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/bin
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project.pros

‎LICENSE.MD‎

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‎Makefile‎

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# Universal C Makefile for MCU targets
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# Path to project root (for top-level, so the project is in ./; first-level, ../; etc.)
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ROOT=.
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# Binary output directory
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BINDIR=$(ROOT)/bin
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# Subdirectories to include in the build
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SUBDIRS=src
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# Nothing below here needs to be modified by typical users
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# Include common aspects of this project
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-include $(ROOT)/common.mk
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ASMSRC:=$(wildcard *.$(ASMEXT))
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ASMOBJ:=$(patsubst %.o,$(BINDIR)/%.o,$(ASMSRC:.$(ASMEXT)=.o))
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HEADERS:=$(wildcard *.$(HEXT))
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CSRC=$(wildcard *.$(CEXT))
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COBJ:=$(patsubst %.o,$(BINDIR)/%.o,$(CSRC:.$(CEXT)=.o))
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CPPSRC:=$(wildcard *.$(CPPEXT))
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CPPOBJ:=$(patsubst %.o,$(BINDIR)/%.o,$(CPPSRC:.$(CPPEXT)=.o))
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OUT:=$(BINDIR)/$(OUTNAME)
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.PHONY: all clean upload _force_look
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# By default, compile program
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all: $(BINDIR) $(OUT)
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# Remove all intermediate object files (remove the binary directory)
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clean:
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-rm -f $(OUT)
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-rm -rf $(BINDIR)
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# Uploads program to device
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upload: all
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$(UPLOAD)
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# Phony force-look target
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_force_look:
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@true
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# Looks in subdirectories for things to make
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$(SUBDIRS): %: _force_look
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@$(MAKE) --no-print-directory -C $@
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# Ensure binary directory exists
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$(BINDIR):
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-@mkdir -p $(BINDIR)
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# Compile program
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$(OUT): $(SUBDIRS) $(ASMOBJ) $(COBJ) $(CPPOBJ)
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@echo LN $(BINDIR)/*.o $(LIBRARIES) to $@
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@$(CC) $(LDFLAGS) $(BINDIR)/*.o $(LIBRARIES) -o $@
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@$(MCUPREFIX)size $(SIZEFLAGS) $(OUT)
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$(MCUPREPARE)
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# Assembly source file management
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$(ASMOBJ): $(BINDIR)/%.o: %.$(ASMEXT) $(HEADERS)
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@echo AS $<
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@$(AS) $(AFLAGS) -o $@ $<
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# Object management
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$(COBJ): $(BINDIR)/%.o: %.$(CEXT) $(HEADERS)
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@echo CC $(INCLUDE) $<
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$(CC) $(INCLUDE) $(CFLAGS) -o $@ $<
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$(CPPOBJ): $(BINDIR)/%.o: %.$(CPPEXT) $(HEADERS)
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@echo CPC $(INCLUDE) $<
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@$(CPPCC) $(INCLUDE) $(CPPFLAGS) -o $@ $<

‎common.mk‎

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# Universal C Makefile for MCU targets
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# Top-level template file to configure build
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MAKE_COMMAND=make
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# Makefile for IFI VeX Cortex Microcontroller (STM32F103VD series)
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DEVICE=VexCortex
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# Libraries to include in the link (use -L and -l) e.g. -lm, -lmyLib
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LIBRARIES=$(wildcard $(ROOT)/firmware/*.a) -lgcc -lm
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# Prefix for ARM tools (must be on the path)
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MCUPREFIX=arm-none-eabi-
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# Flags for the assembler
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MCUAFLAGS=-mthumb -mcpu=cortex-m3 -mlittle-endian
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# Flags for the compiler
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MCUCFLAGS=-mthumb -mcpu=cortex-m3 -mlittle-endian -mfloat-abi=soft
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# Flags for the linker
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MCULFLAGS=-nostartfiles -Wl,-static -Bfirmware -Wl,-u,VectorTable -Wl,-T -Xlinker firmware/cortex.ld
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# Prepares the elf file by converting it to a binary that java can write
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MCUPREPARE=$(OBJCOPY) $(OUT) -O binary $(BINDIR)/$(OUTBIN)
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# Advanced sizing flags
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SIZEFLAGS=
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# Uploads program using java
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UPLOAD=@java -jar firmware/uniflash.jar vex $(BINDIR)/$(OUTBIN)
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# Advanced options
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ASMEXT=s
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CEXT=c
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CPPEXT=cpp
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HEXT=h
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INCLUDE=-I$(ROOT)/include -I$(ROOT)/src
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OUTBIN=output.bin
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OUTNAME=output.elf
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# Flags for programs
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AFLAGS:=$(MCUAFLAGS)
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ARFLAGS:=$(MCUCFLAGS)
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CCFLAGS:=-c -Wall $(MCUCFLAGS) -Os -ffunction-sections -fsigned-char -fomit-frame-pointer -fsingle-precision-constant
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CFLAGS:=$(CCFLAGS) -std=gnu99 -Werror=implicit-function-declaration
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CPPFLAGS:=$(CCFLAGS) -fno-exceptions -fno-rtti -felide-constructors
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LDFLAGS:=-Wall $(MCUCFLAGS) $(MCULFLAGS) -Wl,--gc-sections
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# Tools used in program
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AR:=$(MCUPREFIX)ar
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AS:=$(MCUPREFIX)as
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CC:=$(MCUPREFIX)gcc
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CPPCC:=$(MCUPREFIX)g++
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OBJCOPY:=$(MCUPREFIX)objcopy

‎firmware/STM32F10x.ld‎

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/* Memory space definitions */
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MEMORY {
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 384K
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}
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/* Higher address of the user mode stack */
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EXTERN ( _estack );
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PROVIDE ( _estack = ORIGIN(RAM) + LENGTH(RAM) );
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/* This sends all unreferenced IRQHandlers to reset. */
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PROVIDE ( ISR_SWI = 0 );
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PROVIDE ( ISR_IRQ = 0 );
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PROVIDE ( ISR_Prefetch = 0 );
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PROVIDE ( ISR_Abort = 0 );
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PROVIDE ( ISR_FIQ = 0 );
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PROVIDE ( ISR_NMI = 0 );
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PROVIDE ( ISR_HardFault = 0 );
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PROVIDE ( ISR_MemManage = 0 );
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PROVIDE ( ISR_BusFault = 0 );
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PROVIDE ( ISR_UsageFault = 0 );
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PROVIDE ( ISR_SVC = 0 );
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PROVIDE ( ISR_DebugMon = 0 );
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PROVIDE ( ISR_PendSV = 0 );
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PROVIDE ( ISR_SysTick = 0 );
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PROVIDE ( ISR_WWDG = 0 );
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PROVIDE ( ISR_PVD = 0 );
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PROVIDE ( ISR_TAMPER = 0 );
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PROVIDE ( ISR_RTC = 0 );
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PROVIDE ( ISR_FLASH = 0 );
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PROVIDE ( ISR_RCC = 0 );
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PROVIDE ( ISR_EXTI0 = 0 );
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PROVIDE ( ISR_EXTI1 = 0 );
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PROVIDE ( ISR_EXTI2 = 0 );
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PROVIDE ( ISR_EXTI3 = 0 );
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PROVIDE ( ISR_EXTI4 = 0 );
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PROVIDE ( ISR_DMAChannel1 = 0 );
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PROVIDE ( ISR_DMAChannel2 = 0 );
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PROVIDE ( ISR_DMAChannel3 = 0 );
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PROVIDE ( ISR_DMAChannel4 = 0 );
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PROVIDE ( ISR_DMAChannel5 = 0 );
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PROVIDE ( ISR_DMAChannel6 = 0 );
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PROVIDE ( ISR_DMAChannel7 = 0 );
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PROVIDE ( ISR_DMA1_Channel1 = 0 );
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PROVIDE ( ISR_DMA1_Channel2 = 0 );
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PROVIDE ( ISR_DMA1_Channel3 = 0 );
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PROVIDE ( ISR_DMA1_Channel4 = 0 );
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PROVIDE ( ISR_DMA1_Channel5 = 0 );
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PROVIDE ( ISR_DMA1_Channel6 = 0 );
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PROVIDE ( ISR_DMA1_Channel7 = 0 );
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PROVIDE ( ISR_ADC = 0 );
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PROVIDE ( ISR_ADC1_2 = 0 );
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PROVIDE ( ISR_USB_HP_CAN_TX = 0 );
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PROVIDE ( ISR_USB_HP_CAN1_TX = 0 );
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PROVIDE ( ISR_USB_LP_CAN_RX0 = 0 );
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PROVIDE ( ISR_USB_LP_CAN1_RX0 = 0 );
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PROVIDE ( ISR_CAN_RX1 = 0 );
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PROVIDE ( ISR_CAN1_RX1 = 0 );
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PROVIDE ( ISR_CAN_SCE = 0 );
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PROVIDE ( ISR_CAN1_SCE = 0 );
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PROVIDE ( ISR_EXTI9_5 = 0 );
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PROVIDE ( ISR_TIM1_BRK = 0 );
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PROVIDE ( ISR_TIM1_UP = 0 );
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PROVIDE ( ISR_TIM1_TRG_COM = 0 );
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PROVIDE ( ISR_TIM1_CC = 0 );
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PROVIDE ( ISR_TIM2 = 0 );
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PROVIDE ( ISR_TIM3 = 0 );
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PROVIDE ( ISR_TIM4 = 0 );
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PROVIDE ( ISR_I2C1_EV = 0 );
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PROVIDE ( ISR_I2C1_ER = 0 );
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PROVIDE ( ISR_I2C2_EV = 0 );
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PROVIDE ( ISR_I2C2_ER = 0 );
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PROVIDE ( ISR_SPI1 = 0 );
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PROVIDE ( ISR_SPI2 = 0 );
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PROVIDE ( ISR_USART1 = 0 );
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PROVIDE ( ISR_USART2 = 0 );
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PROVIDE ( ISR_USART3 = 0 );
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PROVIDE ( ISR_EXTI15_10 = 0 );
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PROVIDE ( ISR_RTCAlarm = 0 );
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PROVIDE ( ISR_USBWakeUp = 0 );
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PROVIDE ( ISR_TIM8_BRK = 0 );
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PROVIDE ( ISR_TIM8_UP = 0 );
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PROVIDE ( ISR_TIM8_TRG_COM = 0 );
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PROVIDE ( ISR_TIM8_CC = 0 );
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PROVIDE ( ISR_ADC3 = 0 );
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PROVIDE ( ISR_FSMC = 0 );
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PROVIDE ( ISR_SDIO = 0 );
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PROVIDE ( ISR_TIM5 = 0 );
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PROVIDE ( ISR_SPI3 = 0 );
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PROVIDE ( ISR_UART4 = 0 );
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PROVIDE ( ISR_UART5 = 0 );
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PROVIDE ( ISR_TIM6 = 0 );
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PROVIDE ( ISR_TIM7 = 0 );
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PROVIDE ( ISR_DMA2_Channel1 = 0 );
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PROVIDE ( ISR_DMA2_Channel2 = 0 );
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PROVIDE ( ISR_DMA2_Channel3 = 0 );
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PROVIDE ( ISR_DMA2_Channel4_5 = 0 );

‎firmware/cortex.ld‎

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/* Include STM32F10X linker scripts */
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INCLUDE "STM32F10x.ld"
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EXTERN ( _heapbegin );
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/* Section definitions for Cortex firmware flashing */
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SECTIONS {
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.isr_vector : {
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/* startup code, prevents garbage collection from eating everything */
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} >FLASH
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.text : {
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. = ALIGN(4);
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*(.text)
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*(.text.*)
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/* Preinit array of functions */
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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. = ALIGN(4);
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/* Init array of functions */
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KEEP(*(.init))
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. = ALIGN(4);
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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. = ALIGN(4);
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/* C++ constructors */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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/* Finalizer array of functions */
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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. = ALIGN(4);
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/* C++ destructors */
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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_etext = .;
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_srdata = .;
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. = ALIGN(4);
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*(.rodata)
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_erdata = .;
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_sidata = .;
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} >FLASH
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/* The program executes knowing that the data is in the RAM, but the loader puts the
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* initial values in the FLASH (inidata). The startup copies the initial values over */
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.data : AT ( _sidata ) {
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. = ALIGN(4);
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_sdata = .;
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*(.data)
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*(.data.*)
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*(.RAMtext)
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. = ALIGN(4);
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_edata = .;
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} >RAM
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/* Uninitialized data (zero-fill) section */
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.bss : {
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. = ALIGN(4);
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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. = ALIGN(8);
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_heapbegin = .;
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} >RAM
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/DISCARD/ : {
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libc.a ( * )
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libg.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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libstdc++.a ( * )
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libsupc++.a ( * )
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}
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/* ARM exception unwinding, mandated by ARM EABI C++ standard (with -fno-exceptions?) */
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.ARM.exidx 0 : { *(.ARM.exidx*) }
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/* Stabs debugging sections */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}

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