Clean up AU280 design

Author: alexforencich

example/AU280/fpga_10g/README.md

@@ -6,8 +6,7 @@ This example design targets the Xilinx Alveo U280 FPGA board.
 
 The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
 will echo back any packets received.  The design will also respond correctly
-to ARP requests.  The design also enables the gigabit Ethernet interface for
-testing with a QSFP loopback adapter.  
+to ARP requests.  
 
 *  FPGA: xcu280-fsvh2892-2L-e
 *  PHY: 10G BASE-R PHY IP core and internal GTY transceiver

example/AU280/fpga_10g/fpga/Makefile

@@ -7,7 +7,6 @@ FPGA_ARCH = virtexuplus
 # Files for synthesis
 SYN_FILES = rtl/fpga.v
 SYN_FILES += rtl/fpga_core.v
-SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
 SYN_FILES += lib/eth/rtl/eth_mac_10g.v
@@ -70,7 +69,7 @@ program: $(FPGA_TOP).bit
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
 
-%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
+%.mcs %.prm: %.bit
 	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
 	echo "exit" >> generate_mcs.tcl
 	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
@@ -83,16 +82,16 @@ program: $(FPGA_TOP).bit
 	do cp $*$$x rev/$*_rev$$COUNT$$x; \
 	echo "Output: rev/$*_rev$$COUNT$$x"; done;
 
-flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "open_hw" > flash.tcl
 	echo "connect_hw_server" >> flash.tcl
 	echo "open_hw_target" >> flash.tcl
 	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
 	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
 	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
 	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
-	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
-	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
 	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl

example/AU280/fpga_10g/rtl/debounce_switch.v

@@ -182,44 +182,7 @@ sync_reset_125mhz_inst (
 );
 
 // GPIO
-wire [3:0] sw_int;
-
-debounce_switch #(
-    .WIDTH(4),
-    .N(4),
-    .RATE(156000)
-)
-debounce_switch_inst (
-    .clk(clk_156mhz_int),
-    .rst(rst_156mhz_int),
-    .in({sw}),
-    .out({sw_int})
-);
-
-wire uart_txd_int;
-
-sync_signal #(
-    .WIDTH(1),
-    .N(2)
-)
-sync_signal_inst (
-    .clk(clk_156mhz_int),
-    .in({uart_txd}),
-    .out({uart_txd_int})
-);
-
-// SI570 I2C
-wire i2c_scl_i;
-wire i2c_scl_o = 1'b1;
-wire i2c_scl_t = 1'b1;
-wire i2c_sda_i;
-wire i2c_sda_o = 1'b1;
-wire i2c_sda_t = 1'b1;
-
-assign i2c_scl_i = i2c_scl;
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda_i = i2c_sda;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign hbm_cattrip = 1'b0;
 
 // XGMII 10G PHY
 assign qsfp0_refclk_oe_b = 1'b0;