Merge AU200, AU250, and VCU1525 designs

Signed-off-by: Alex Forencich <[email protected]>

Author: alexforencich

example/AU200/fpga_25g/README.md

@@ -1,29 +1,28 @@
-# Verilog Ethernet Alveo U200 Example Design
+# Verilog Ethernet Alveo U200/Alveo U250/VCU1525 Example Design
 
 ## Introduction
 
-This example design targets the Xilinx Alveo U200 FPGA board.
+This example design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
 
-The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
-will echo back any packets received.  The design will also respond correctly
-to ARP requests.
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received.  The design will also respond correctly to ARP requests.
 
-*  FPGA: xcu200-fsgd2104-2-e
-*  PHY: 10G BASE-R PHY IP core and internal GTY transceiver
+* FPGA
+  * AU200: xcu200-fsgd2104-2-e
+  * AU250: xcu250-fsgd2104-2-e
+  * VCU1525: xcvu9p-fsgd2104-2L-e
+* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
 
 ## How to build
 
-Run make to build.  Ensure that the Xilinx Vivado toolchain components are
-in PATH.  
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are in PATH.
 
 ## How to test
 
-Run make program to program the Alveo U200 board with Vivado.  Then run
+Run make program to program the FPGA board with Vivado.  Then run
 
     netcat -u 192.168.1.128 1234
 
-to open a UDP connection to port 1234.  Any text entered into netcat will be
-echoed back after pressing enter.
+to open a UDP connection to port 1234.  Any text entered into netcat will be echoed back after pressing enter.
 
 It is also possible to use hping to test the design by running
 

example/AU200/fpga_25g/fpga.xdc

@@ -1,5 +1,7 @@
-# XDC constraints for the Xilinx Alveo U200 board
-# part: xcu200-fsgd2104-2-e
+# XDC constraints for Xilinx AU200/AU250/VCU1525
+# AU200 part: xcu200-fsgd2104-2-e
+# AU250 part: xcu250-figd2104-2-e
+# VCU1525 part: xcvu9p-fsgd2104-2L-e
 
 # General configuration
 set_property CFGBVS GND                                [current_design]

example/AU200/fpga_25g/fpga/Makefile …ample/AU200/fpga_25g/fpga_AU200/Makefileexample/AU200/fpga_25g/fpga/Makefile renamed to example/AU200/fpga_25g/fpga_AU200/Makefile example/AU200/fpga_25g/fpga/Makefile renamed to example/AU200/fpga_25g/fpga_AU200/Makefile

@@ -112,4 +112,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-

example/AU200/fpga_25g/fpga/config.tcl …ple/AU200/fpga_25g/fpga_AU200/config.tclexample/AU200/fpga_25g/fpga/config.tcl renamed to example/AU200/fpga_25g/fpga_AU200/config.tcl example/AU200/fpga_25g/fpga/config.tcl renamed to example/AU200/fpga_25g/fpga_AU200/config.tcl

@@ -112,4 +112,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-

example/AU200/fpga_25g/fpga_10g/Makefile …e/AU200/fpga_25g/fpga_AU200_10g/Makefileexample/AU200/fpga_25g/fpga_10g/Makefile renamed to example/AU200/fpga_25g/fpga_AU200_10g/Makefile example/AU200/fpga_25g/fpga_10g/Makefile renamed to example/AU200/fpga_25g/fpga_AU200_10g/Makefile

@@ -112,4 +112,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-

…ample/AU200/fpga_25g/fpga_10g/config.tcl …AU200/fpga_25g/fpga_AU200_10g/config.tclexample/AU200/fpga_25g/fpga_10g/config.tcl renamed to example/AU200/fpga_25g/fpga_AU200_10g/config.tcl example/AU200/fpga_25g/fpga_10g/config.tcl renamed to example/AU200/fpga_25g/fpga_AU200_10g/config.tcl

@@ -112,4 +112,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-