Add KR260 reference design example

Signed-off-by: Víctor Mayoral Vilches <[email protected]>

Author: vmayoral

example/KR260/fpga/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

example/KR260/fpga/README.md

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+# Verilog Ethernet KR260 Example Design
+
+## Introduction
+
+This example design targets the AMD KR260 FPGA SoC board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+*  FPGA: `XCK26-SFVC784-2LV-C` (or `-I`, if industrial-grade)
+*  PHY: 10G BASE-R PHY IP core and internal GTY transceiver
+
+## How to build
+
+:warning: *<ins>To generate the bitstream for the reference design example here
+you need a Vivado license</ins>*. In case you don't have it, you can either
+fetch it from [here](https://www.xilinx.com/support/licensing_solution_center.html)
+or use the the default "30 day evaluation license"  that comes with Vivado default
+installation.
+
+Run `make` to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.
+
+## How to test
+
+Program the KR260 board with Vivado's Hardware Device Manager (via JTAG). Connect the KR260 SFP+ port to a 10G Ethernet NIC in your host. Then run in your host machine:
+
+    netcat -u 192.168.1.128 1234
+
+to open a UDP connection to port 1234.  Any text entered into netcat will be
+echoed back after pressing enter.
+
+It is also possible to use hping to test the design by running
+
+    hping 192.168.1.128 -2 -p 1234 -d 1024

example/KR260/fpga/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi

example/KR260/fpga/fpga.xdc

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+# XDC constraints for the AMD KR260 board
+# part: XCK26-SFVC784-2LV-C/I
+
+# General configuration
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+
+# System clocks
+# 125 MHz
+#
+# The 125 MHz clock signal is a standard reference clock frequency used 
+# in many Ethernet PHYs. This clock signal is used as a timing reference 
+# for the PHY's internal circuitry, including the serializer/deserializer 
+# (SERDES) components that convert digital data to analog signals for 
+# transmission over the physical medium and vice versa. The SERDES components 
+# require a precise clock signal to ensure accurate timing of the transmitted 
+# and received data.
+#
+# NOTE: the GTH transceivers need a free-running clock.
+#
+
+# # Option 1: use the 125 MHz clock from the U87 chip
+# # GTR pins, connected to the PS, cannot use directly
+# set_property -dict {LOC C47  IOSTANDARD LVDS_25} [get_ports clk_125mhz_p]
+# set_property -dict {LOC C48  IOSTANDARD LVDS_25} [get_ports clk_125mhz_n]
+# create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
+
+# # Option 2: use the 156.25 MHz MGT reference clock
+# # GTH pins, connected to the PL, however:
+# # 
+# # The MGT (Multi-Gigabit Transceiver) reference clock inputs and GTH (Gigabit Transceiver) 
+# # pins are designed for different types of clock signals, and connecting them together can 
+# # result in damage to the circuitry or a non-functioning design.
+# # 
+# # Connecting the MGT reference clock inputs to GTH pins can result in damage to the 
+# # circuitry or a non-functioning design because the MGT reference clock signal has different 
+# # voltage and timing requirements than the GTH system clock. The MGT reference clock signal 
+# # requires a dedicated input buffer, such as the IBUFDS_GTE2 or IBUFDS_GTH, to properly 
+# # receive the clock signal and perform the necessary signal conditioning before it can be 
+# # used by the MGT transceiver. The GTH pins, on the other hand, require a specific input 
+# # buffer, such as the IBUFDS_GTE2 or IBUFDS_GTH, to properly receive the system clock signal 
+# # and perform the necessary signal conditioning before it can be used for data transfer.
+# # 
+# set_property -dict {LOC Y6 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p] ;# GTH_REFCLK0_C2M_P via U90, SOM240_2 C3
+# set_property -dict {LOC Y5 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n] ;# GTH_REFCLK0_C2M_N via U90, SOM240_2 C4
+# create_clock -period 6.400 -name clk_125mhz [get_ports clk_125mhz_p]
+
+# Option 3: use the 25 MHz clock outputs to the PL from U91
+# and feed that into a PLL to convert it to 125 MHz
+set_property -dict {LOC C3 IOSTANDARD LVCMOS18} [get_ports clk_25mhz_ref] ;# HPA_CLK0P_CLK, HPA_CLK0_P, via U91, SOM240_1 A6
+create_clock -period 40.000 -name clk_25mhz [get_ports clk_25mhz_ref]
+
+# LEDs
+set_property -dict {LOC F8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]  ;# HPA14P, HPA14_P, som240_1_d13, VCCO - som240_1_d1
+set_property -dict {LOC E8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]  ;# HPA14N, HPA14_N, som240_1_d14, VCCO - som240_1_d1
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# # Reset button
+# # PS_POR_L, note schematics hints C15 is PS_POR_B (Power-on Reset) signal
+# # whereas the "Kria SOM Carrier Card Design Guide" says C15 is PS_POR_L.
+# #
+# # Signal is pulled up to 1.8V through a 4.70 KΩ resistor on the SOM, LVCMOS18
+# #
+# # NOTE: Connected to the PS, not accessible to the PL
+# # 
+# # see https://docs.xilinx.com/r/en-US/ug1091-carrier-card-design/Sideband-Signals
+# set_property -dict {LOC P16 IOSTANDARD LVCMOS18} [get_ports reset]  ;# som240_1_c15, PS_POR_B, PS_POR_L
+#
+# set_false_path -from [get_ports {reset}]
+# set_input_delay 0 [get_ports {reset}]
+
+# No push buttons in KR260
+# FWEN is used for other features
+#
+# set_property -dict {LOC AG15 IOSTANDARD LVCMOS33} [get_ports btnu]
+# set_property -dict {LOC AF15 IOSTANDARD LVCMOS33} [get_ports btnl]
+# set_property -dict {LOC AE15 IOSTANDARD LVCMOS33} [get_ports btnd]
+# set_property -dict {LOC AE14 IOSTANDARD LVCMOS33} [get_ports btnr]
+# set_property -dict {LOC AG13 IOSTANDARD LVCMOS33} [get_ports btnc]
+#
+# set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
+# set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
+
+# No DIP switches in KR260
+#
+# set_property -dict {LOC AN14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
+#
+# set_false_path -from [get_ports {sw[*]}]
+# set_input_delay 0 [get_ports {sw[*]}]
+
+# No PL-Side UART available from default banks
+#
+# set_property -dict {LOC F13  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
+# set_property -dict {LOC E13  IOSTANDARD LVCMOS33} [get_ports uart_rxd]
+# set_property -dict {LOC D12  IOSTANDARD LVCMOS33} [get_ports uart_rts]
+# set_property -dict {LOC E12  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
+#
+# set_false_path -to [get_ports {uart_txd uart_cts}]
+# set_output_delay 0 [get_ports {uart_txd uart_cts}]
+# set_false_path -from [get_ports {uart_rxd uart_rts}]
+# set_input_delay 0 [get_ports {uart_rxd uart_rts}]
+
+# No PL-I2C interfaces
+#set_property -dict {LOC J10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]
+#set_property -dict {LOC K20  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_scl]
+#set_property -dict {LOC L20  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_sda]
+
+#set_false_path -to [get_ports {i2c1_sda i2c1_scl}]
+#set_output_delay 0 [get_ports {i2c1_sda i2c1_scl}]
+#set_false_path -from [get_ports {i2c1_sda i2c1_scl}]
+#set_input_delay 0 [get_ports {i2c1_sda i2c1_scl}]
+
+# SFP+ Interface
+set_property -dict {LOC T2 } [get_ports sfp0_rx_p] ;# GTH_DP2_C2M_P, som240_2_b1
+set_property -dict {LOC T1 } [get_ports sfp0_rx_n] ;# GTH_DP2_C2M_N, som240_2_b2
+set_property -dict {LOC R4 } [get_ports sfp0_tx_p] ;# GTH_DP2_M2C_P, som240_2_b5
+set_property -dict {LOC R3 } [get_ports sfp0_tx_n] ;# GTH_DP2_M2C_N, som240_2_b6
+
+set_property -dict {LOC Y6 } [get_ports sfp_mgt_refclk_0_p] ;# GTH_REFCLK0_C2M_P via U90, SOM240_2 C3
+set_property -dict {LOC Y5 } [get_ports sfp_mgt_refclk_0_n] ;# GTH_REFCLK0_C2M_N via U90, SOM240_2 C4
+set_property -dict {LOC Y10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 } [get_ports sfp0_tx_disable_b]  ;# HDB19, SOM240_2_A47
+
+# 156.25 MHz MGT reference clock
+create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
+
+set_false_path -to [get_ports {sfp0_tx_disable_b}]
+set_output_delay 0 [get_ports {sfp0_tx_disable_b}]

example/KR260/fpga/fpga/Makefile

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+
+# FPGA settings
+FPGA_PART = XCK26-SFVC784-2LV-C
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete_64.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
+SYN_FILES += lib/eth/rtl/udp_64.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
+SYN_FILES += lib/eth/rtl/ip_complete_64.v
+SYN_FILES += lib/eth/rtl/ip_64.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+
+# IP
+IP_TCL_FILES += ip/eth_xcvr_gt.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+