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Add zynq_ps to KR260 10g example design
Signed-off-by: Víctor Mayoral Vilches <[email protected]>
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‎example/KR260/fpga_10g/fpga/Makefile‎

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@@ -57,6 +57,7 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES += ip/eth_xcvr_gt.tcl
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IP_TCL_FILES += ip/zynq_ps.tcl
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include ../common/vivado.mk
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‎example/KR260/fpga_10g/ip/zynq_ps.tcl‎

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# Copyright 2022, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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# create block design
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create_bd_design "zynq_ps"
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# Create blocks
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# Zynq PS
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set zynq_ultra_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps ]
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set_property -dict [list \
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CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
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CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
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CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
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CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
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CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 \
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CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
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CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
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CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
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CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
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CONFIG.PSU__DDRC__T_RC {46.5} \
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CONFIG.PSU__DDRC__T_FAW {21.0} \
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CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
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CONFIG.PSU__DDRC__FREQ_MHZ {1067} \
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CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__PMU__GPI0__ENABLE {1} \
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CONFIG.PSU__PMU__GPI1__ENABLE {0} \
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CONFIG.PSU__PMU__GPI2__ENABLE {0} \
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CONFIG.PSU__PMU__GPI3__ENABLE {0} \
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CONFIG.PSU__PMU__GPI4__ENABLE {0} \
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CONFIG.PSU__PMU__GPI5__ENABLE {0} \
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CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
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CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
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CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
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CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
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CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
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CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
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CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
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CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
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CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
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CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
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CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
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CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
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CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
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CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
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CONFIG.PSU__DP__LANE_SEL {Single Lower} \
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CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
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CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
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CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
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CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
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CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
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CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x04} \
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CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__USE__M_AXI_GP0 {1} \
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CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
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CONFIG.PSU__USE__M_AXI_GP1 {0} \
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CONFIG.PSU__USE__M_AXI_GP2 {0} \
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CONFIG.PSU__USE__S_AXI_GP0 {1} \
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CONFIG.PSU__USE__IRQ0 {1} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {667} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
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CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {667} \
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CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
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CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {300} \
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CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
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] $zynq_ultra_ps
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# control AXI interconnect
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set axi_interconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_ctrl ]
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# reset
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set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset ]
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# Create connections
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# Clock
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set pl_clk0 [get_bd_pins $zynq_ultra_ps/pl_clk0]
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make_bd_pins_external $pl_clk0
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set_property name pl_clk0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
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set pl_clk0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
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connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/maxihpm0_fpd_aclk]
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connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/saxihpc0_fpd_aclk]
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connect_bd_net $pl_clk0 [get_bd_pins $proc_sys_reset/slowest_sync_clk]
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connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/ACLK]
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connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/S00_ACLK]
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connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M00_ACLK]
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connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M01_ACLK]
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set pl_clk0_busif [list]
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# Reset
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set pl_resetn0 [get_bd_pins $zynq_ultra_ps/pl_resetn0]
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connect_bd_net $pl_resetn0 [get_bd_pins $proc_sys_reset/ext_reset_in]
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set pl_reset [get_bd_pins $proc_sys_reset/peripheral_reset]
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make_bd_pins_external $pl_reset
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set_property name pl_reset [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_reset]]
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set interconnect_aresetn [get_bd_pins $proc_sys_reset/interconnect_aresetn]
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connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/ARESETN]
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connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/S00_ARESETN]
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connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M00_ARESETN]
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connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M01_ARESETN]
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# MMIO
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connect_bd_intf_net [get_bd_intf_pins $zynq_ultra_ps/M_AXI_HPM0_FPD] [get_bd_intf_pins $axi_interconnect_ctrl/S00_AXI]
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# Control interface
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set m_axil_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M00_AXI]
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make_bd_intf_pins_external $m_axil_ctrl_pin
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set_property name m_axil_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
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set m_axil_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
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set_property -dict [list \
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CONFIG.PROTOCOL AXI4LITE \
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CONFIG.DATA_WIDTH 32 \
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CONFIG.ADDR_WIDTH 24 \
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] $m_axil_ctrl_port
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lappend pl_clk0_busif $m_axil_ctrl_port
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# Application control interface
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set m_axil_app_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M01_AXI]
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make_bd_intf_pins_external $m_axil_app_ctrl_pin
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set_property name m_axil_app_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
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set m_axil_app_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
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set_property -dict [list \
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CONFIG.PROTOCOL AXI4LITE \
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CONFIG.DATA_WIDTH 32 \
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CONFIG.ADDR_WIDTH 24 \
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] $m_axil_app_ctrl_port
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lappend pl_clk0_busif $m_axil_app_ctrl_port
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# DMA interface
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set s_axi_dma_pin [get_bd_intf_pins $zynq_ultra_ps/S_AXI_HPC0_FPD]
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make_bd_intf_pins_external $s_axi_dma_pin
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set_property name s_axi_dma [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
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set s_axi_dma_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
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lappend pl_clk0_busif $s_axi_dma_port
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# IRQ
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set pl_ps_irq0 [get_bd_pins $zynq_ultra_ps/pl_ps_irq0]
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make_bd_pins_external $pl_ps_irq0
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set_property name pl_ps_irq0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
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set pl_ps_irq0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
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set_property -dict [list \
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CONFIG.PortWidth 8 \
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] $pl_ps_irq0_port
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# Port clock associations
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set lst [list]
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foreach port $pl_clk0_busif {
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lappend lst [get_property name $port]
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}
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set_property CONFIG.ASSOCIATED_BUSIF [join $lst ":"] $pl_clk0_port
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# Assign addresses
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assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_HIGH] -force
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assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_QSPI] -force
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assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_LOW] -force
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assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_LPS_OCM] -force
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assign_bd_address -offset 0xA000_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_ctrl_port/Reg] -force
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assign_bd_address -offset 0xA800_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_app_ctrl_port/Reg] -force
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validate_bd_design
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# Save block design
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save_bd_design [current_bd_design]
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close_bd_design [current_bd_design]

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