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Add makefiles for VU13P variant of HTG-9200
Signed-off-by: Alex Forencich <[email protected]>
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‎example/HTG9200/fpga_25g/README.md‎

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@@ -8,7 +8,7 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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* FPGA: xcvu9p-flgb2104-2-e
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* FPGA: xcvu9p-flgb2104-2-e or xcvu13p-fhgb2104-2-e
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* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build

‎example/HTG9200/fpga_25g/fpga.xdc‎

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# XDC constraints for the HiTech Global HTG-9200 board
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# part: xcvu9p-flgb2104-2-e
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# part: xcvu13p-fhgb2104-2-e
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# General configuration
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set_property CFGBVS GND [current_design]

‎example/HTG9200/fpga_25g/fpga_10g_vu13p/Makefile‎

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# FPGA settings
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FPGA_PART = xcvu13p-fhgb2104-2-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/i2c_master.v
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SYN_FILES += pll/si5341_i2c_init.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES += ip/eth_xcvr_gt.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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example/HTG9200/fpga_25g/fpga_10g/config.tcl renamed to example/HTG9200/fpga_25g/fpga_10g_vu13p/config.tcl

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example/HTG9200/fpga_25g/fpga/Makefile renamed to example/HTG9200/fpga_25g/fpga_10g_vu9p/Makefile

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example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl renamed to example/HTG9200/fpga_25g/fpga_10g_vu9p/config.tcl

File renamed without changes.

‎example/HTG9200/fpga_25g/fpga_vu13p/Makefile‎

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# FPGA settings
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FPGA_PART = xcvu13p-fhgb2104-2-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/i2c_master.v
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SYN_FILES += pll/si5341_i2c_init.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES += ip/eth_xcvr_gt.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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example/HTG9200/fpga_25g/fpga/config.tcl renamed to example/HTG9200/fpga_25g/fpga_vu13p/config.tcl

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example/HTG9200/fpga_25g/fpga_10g/Makefile renamed to example/HTG9200/fpga_25g/fpga_vu9p/Makefile

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example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl renamed to example/HTG9200/fpga_25g/fpga_vu9p/config.tcl

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