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Add VCU118 + HTG 6x QSFP28 example design
Signed-off-by: Alex Forencich <[email protected]>
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‎example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md‎

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# Verilog Ethernet VCU118 + HTG 6x QSFP28 FMC+ Example Design
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## Introduction
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This example design targets the Xilinx VCU118 FPGA board with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J2.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter.
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The design is configured to run all 8 QSFP28 modules synchronous to the QSFP Si570 (U38) on the VCU118. This is done by forwarding the MGT reference clock for QSFP1 through the FPGA to the SYNC_C2M pins on the FMC+, which is connected as a reference input to the Si5341 PLL (U7) on the FMC+.
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* FPGA: xcvu9p-flga2104-2L-e
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* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run make program to program the VCU118 board with Vivado. Then run
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netcat -u 192.168.1.128 1234
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to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter.
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It is also possible to use hping to test the design by running
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hping 192.168.1.128 -2 -p 1234 -d 1024
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Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 25G data path between the 25G MAC and 25G PHY so that the 25G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to insert the gigabit port into the 25G data path, or off to bypass the gigabit port. Turn on SW12.2 to place the port in the TX path or off to place the port in the RX path.

‎example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk‎

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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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ifdef XDC_FILES
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XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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else
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XDC_FILES_REL = $(PROJECT).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi

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