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Remove debounce_switch and clean up code
Signed-off-by: Víctor Mayoral Vilches <[email protected]>
1 parent ee97f7a commit d1c11af

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‎example/KR260/fpga/fpga.xdc‎

Lines changed: 1 addition & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -5,46 +5,8 @@
55
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
66

77
# System clocks
8-
# 125 MHz
98
#
10-
# The 125 MHz clock signal is a standard reference clock frequency used
11-
# in many Ethernet PHYs. This clock signal is used as a timing reference
12-
# for the PHY's internal circuitry, including the serializer/deserializer
13-
# (SERDES) components that convert digital data to analog signals for
14-
# transmission over the physical medium and vice versa. The SERDES components
15-
# require a precise clock signal to ensure accurate timing of the transmitted
16-
# and received data.
17-
#
18-
# NOTE: the GTH transceivers need a free-running clock.
19-
#
20-
21-
# # Option 1: use the 125 MHz clock from the U87 chip
22-
# # GTR pins, connected to the PS, cannot use directly
23-
# set_property -dict {LOC C47 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p]
24-
# set_property -dict {LOC C48 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n]
25-
# create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
26-
27-
# # Option 2: use the 156.25 MHz MGT reference clock
28-
# # GTH pins, connected to the PL, however:
29-
# #
30-
# # The MGT (Multi-Gigabit Transceiver) reference clock inputs and GTH (Gigabit Transceiver)
31-
# # pins are designed for different types of clock signals, and connecting them together can
32-
# # result in damage to the circuitry or a non-functioning design.
33-
# #
34-
# # Connecting the MGT reference clock inputs to GTH pins can result in damage to the
35-
# # circuitry or a non-functioning design because the MGT reference clock signal has different
36-
# # voltage and timing requirements than the GTH system clock. The MGT reference clock signal
37-
# # requires a dedicated input buffer, such as the IBUFDS_GTE2 or IBUFDS_GTH, to properly
38-
# # receive the clock signal and perform the necessary signal conditioning before it can be
39-
# # used by the MGT transceiver. The GTH pins, on the other hand, require a specific input
40-
# # buffer, such as the IBUFDS_GTE2 or IBUFDS_GTH, to properly receive the system clock signal
41-
# # and perform the necessary signal conditioning before it can be used for data transfer.
42-
# #
43-
# set_property -dict {LOC Y6 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p] ;# GTH_REFCLK0_C2M_P via U90, SOM240_2 C3
44-
# set_property -dict {LOC Y5 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n] ;# GTH_REFCLK0_C2M_N via U90, SOM240_2 C4
45-
# create_clock -period 6.400 -name clk_125mhz [get_ports clk_125mhz_p]
46-
47-
# Option 3: use the 25 MHz clock outputs to the PL from U91
9+
# use the 25 MHz clock outputs to the PL from U91
4810
# and feed that into a PLL to convert it to 125 MHz
4911
set_property -dict {LOC C3 IOSTANDARD LVCMOS18} [get_ports clk_25mhz_ref] ;# HPA_CLK0P_CLK, HPA_CLK0_P, via U91, SOM240_1 A6
5012
create_clock -period 40.000 -name clk_25mhz [get_ports clk_25mhz_ref]
@@ -56,62 +18,6 @@ set_property -dict {LOC E8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {le
5618
set_false_path -to [get_ports {led[*]}]
5719
set_output_delay 0 [get_ports {led[*]}]
5820

59-
# # Reset button
60-
# # PS_POR_L, note schematics hints C15 is PS_POR_B (Power-on Reset) signal
61-
# # whereas the "Kria SOM Carrier Card Design Guide" says C15 is PS_POR_L.
62-
# #
63-
# # Signal is pulled up to 1.8V through a 4.70 KΩ resistor on the SOM, LVCMOS18
64-
# #
65-
# # NOTE: Connected to the PS, not accessible to the PL
66-
# #
67-
# # see https://docs.xilinx.com/r/en-US/ug1091-carrier-card-design/Sideband-Signals
68-
# set_property -dict {LOC P16 IOSTANDARD LVCMOS18} [get_ports reset] ;# som240_1_c15, PS_POR_B, PS_POR_L
69-
#
70-
# set_false_path -from [get_ports {reset}]
71-
# set_input_delay 0 [get_ports {reset}]
72-
73-
# No push buttons in KR260
74-
# FWEN is used for other features
75-
#
76-
# set_property -dict {LOC AG15 IOSTANDARD LVCMOS33} [get_ports btnu]
77-
# set_property -dict {LOC AF15 IOSTANDARD LVCMOS33} [get_ports btnl]
78-
# set_property -dict {LOC AE15 IOSTANDARD LVCMOS33} [get_ports btnd]
79-
# set_property -dict {LOC AE14 IOSTANDARD LVCMOS33} [get_ports btnr]
80-
# set_property -dict {LOC AG13 IOSTANDARD LVCMOS33} [get_ports btnc]
81-
#
82-
# set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
83-
# set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
84-
85-
# No DIP switches in KR260
86-
#
87-
# set_property -dict {LOC AN14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
88-
#
89-
# set_false_path -from [get_ports {sw[*]}]
90-
# set_input_delay 0 [get_ports {sw[*]}]
91-
92-
# No PL-Side UART available from default banks
93-
#
94-
# set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
95-
# set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
96-
# set_property -dict {LOC D12 IOSTANDARD LVCMOS33} [get_ports uart_rts]
97-
# set_property -dict {LOC E12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
98-
#
99-
# set_false_path -to [get_ports {uart_txd uart_cts}]
100-
# set_output_delay 0 [get_ports {uart_txd uart_cts}]
101-
# set_false_path -from [get_ports {uart_rxd uart_rts}]
102-
# set_input_delay 0 [get_ports {uart_rxd uart_rts}]
103-
104-
# No PL-I2C interfaces
105-
#set_property -dict {LOC J10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
106-
#set_property -dict {LOC J11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]
107-
#set_property -dict {LOC K20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_scl]
108-
#set_property -dict {LOC L20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_sda]
109-
110-
#set_false_path -to [get_ports {i2c1_sda i2c1_scl}]
111-
#set_output_delay 0 [get_ports {i2c1_sda i2c1_scl}]
112-
#set_false_path -from [get_ports {i2c1_sda i2c1_scl}]
113-
#set_input_delay 0 [get_ports {i2c1_sda i2c1_scl}]
114-
11521
# SFP+ Interface
11622
set_property -dict {LOC T2 } [get_ports sfp0_rx_p] ;# GTH_DP2_C2M_P, som240_2_b1
11723
set_property -dict {LOC T1 } [get_ports sfp0_rx_n] ;# GTH_DP2_C2M_N, som240_2_b2

‎example/KR260/fpga/rtl/fpga.v‎

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -33,14 +33,6 @@ THE SOFTWARE.
3333
* FPGA top-level module
3434
*/
3535
module fpga (
36-
/*
37-
* Clock: 125MHz LVDS
38-
* Reset: Push button, active low
39-
*/
40-
// input wire clk_125mhz_p,
41-
// input wire clk_125mhz_n,
42-
// input wire reset,
43-
4436
/*
4537
* Clock: 25 MHz LVCMOS18
4638
*/
@@ -49,22 +41,8 @@ module fpga (
4941
/*
5042
* GPIO
5143
*/
52-
// input wire btnu,
53-
// input wire btnl,
54-
// input wire btnd,
55-
// input wire btnr,
56-
// input wire btnc,
57-
// input wire [7:0] sw,
5844
output wire [1:0] led,
5945

60-
// /*
61-
// * UART: 115200 bps, 8N1
62-
// */
63-
// input wire uart_rxd,
64-
// output wire uart_txd,
65-
// input wire uart_rts,
66-
// output wire uart_cts,
67-
6846
/*
6947
* Ethernet: SFP+
7048
*/
@@ -78,9 +56,6 @@ module fpga (
7856
);
7957

8058
// Clock and reset
81-
82-
// wire clk_125mhz_ibufg;
83-
// wire clk_125mhz_bufg;
8459
wire clk_25mhz_bufg;
8560

8661
// Internal 125 MHz clock
@@ -97,22 +72,6 @@ wire mmcm_locked;
9772
wire mmcm_clkfb;
9873

9974

100-
// // IBUFGDS stands for Input Buffer Differential Signaling.
101-
// // It is a primitive module in Verilog that is used to buffer
102-
// // an input signal and convert it from a single-ended signal
103-
// // to a differential signal.
104-
// //
105-
// // See https://docs.xilinx.com/r/2022.1-English/ug974-vivado-ultrascale-libraries/IBUFDS
106-
// IBUFGDS #(
107-
// .DIFF_TERM("FALSE"),
108-
// .IBUF_LOW_PWR("FALSE")
109-
// )
110-
// clk_125mhz_ibufg_inst (
111-
// .O (clk_125mhz_ibufg),
112-
// .I (clk_125mhz_p),
113-
// .IB (clk_125mhz_n)
114-
// );
115-
11675
// BUFG stands for "buffer gate." The BUFG primitive is used to create a
11776
// buffer gate, which is a digital circuit component that is used to
11877
// amplify and/or isolate a signal.
@@ -122,11 +81,6 @@ wire mmcm_clkfb;
12281
// with minimal delay.
12382
//
12483
// https://docs.xilinx.com/r/2022.1-English/ug974-vivado-ultrascale-libraries/BUFG
125-
// BUFG
126-
// clk_125mhz_bufg_in_inst (
127-
// .I(clk_125mhz_ibufg),
128-
// .O(clk_125mhz_bufg)
129-
// );
13084
BUFG
13185
clk_25mhz_bufg_in_inst (
13286
.I(clk_25mhz_ref),
@@ -214,61 +168,9 @@ sync_reset_125mhz_inst (
214168
.out(rst_125mhz_int)
215169
);
216170

217-
// GPIO
218-
// wire btnu_int;
219-
// wire btnl_int;
220-
// wire btnd_int;
221-
// wire btnr_int;
222-
// wire btnc_int;
223-
// wire [7:0] sw_int;
224-
225-
// since there's no "in", nor "out"
226-
// debounce_switch doesn't make sense
227-
//
228-
// debounce_switch #(
229-
// .WIDTH(9),
230-
// .N(8),
231-
// .RATE(156000)
232-
// )
233-
// debounce_switch_inst (
234-
// .clk(clk_156mhz_int),
235-
// .rst(rst_156mhz_int),
236-
// .in({
237-
// // btnu,
238-
// // btnl,
239-
// // btnd,
240-
// // btnr,
241-
// // btnc,
242-
// // sw
243-
// }),
244-
// .out({
245-
// // btnu_int,
246-
// // btnl_int,
247-
// // btnd_int,
248-
// // btnr_int,
249-
// // btnc_int,
250-
// // sw_int
251-
// })
252-
// );
253-
254-
// wire uart_rxd_int;
255-
// wire uart_rts_int;
256-
257-
// sync_signal #(
258-
// .WIDTH(2),
259-
// .N(2)
260-
// )
261-
// sync_signal_inst (
262-
// .clk(clk_156mhz_int),
263-
// .in({uart_rxd, uart_rts}),
264-
// .out({uart_rxd_int, uart_rts_int})
265-
// );
266171

267172
// XGMII 10G PHY
268173
assign sfp0_tx_disable_b = 1'b1;
269-
// assign sfp1_tx_disable_b = 1'b1;
270-
// assign sfp2_tx_disable_b = 1'b1;
271-
// assign sfp3_tx_disable_b = 1'b1;
272174

273175
wire sfp0_tx_clk_int;
274176
wire sfp0_tx_rst_int;
@@ -283,9 +185,6 @@ assign clk_156mhz_int = sfp0_tx_clk_int;
283185
assign rst_156mhz_int = sfp0_tx_rst_int;
284186

285187
wire sfp0_rx_block_lock;
286-
// wire sfp1_rx_block_lock;
287-
// wire sfp2_rx_block_lock;
288-
// wire sfp3_rx_block_lock;
289188

290189
wire sfp_mgt_refclk_0;
291190

@@ -366,20 +265,7 @@ core_inst (
366265
/*
367266
* GPIO
368267
*/
369-
// .btnu(btnu_int),
370-
// .btnl(btnl_int),
371-
// .btnd(btnd_int),
372-
// .btnr(btnr_int),
373-
// .btnc(btnc_int),
374-
// .sw(sw_int),
375268
.led(led),
376-
/*
377-
* UART: 115200 bps, 8N1
378-
*/
379-
// .uart_rxd(uart_rxd_int),
380-
// .uart_txd(uart_txd),
381-
// .uart_rts(uart_rts_int),
382-
// .uart_cts(uart_cts),
383269
/*
384270
* Ethernet: SFP+
385271
*/

‎example/KR260/fpga/rtl/fpga_core.v‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -44,22 +44,8 @@ module fpga_core
4444
/*
4545
* GPIO
4646
*/
47-
// input wire btnu,
48-
// input wire btnl,
49-
// input wire btnd,
50-
// input wire btnr,
51-
// input wire btnc,
52-
// input wire [7:0] sw,
5347
output wire [1:0] led,
5448

55-
// /*
56-
// * UART: 115200 bps, 8N1
57-
// */
58-
// input wire uart_rxd,
59-
// output wire uart_txd,
60-
// input wire uart_rts,
61-
// output wire uart_cts,
62-
6349
/*
6450
* Ethernet: SFP+
6551
*/

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