Improve PTP CDC module testbench

alexforencich · alexforencich · commit f9ae6da8bd4e · 2023-09-23T14:33:14.000-07:00
Signed-off-by: Alex Forencich &lt;alex@alexforencich.com&gt;
diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v
@@ -25,7 +25,7 @@ THE SOFTWARE.
 // Language: Verilog 2001
 
 `resetall
-`timescale 1ns / 1ps
+`timescale 1ns / 1fs
 `default_nettype none
 
 /*
diff --git a/tb/ptp_clock_cdc/Makefile b/tb/ptp_clock_cdc/Makefile
@@ -24,7 +24,7 @@ SIM ?= icarus
 WAVES ?= 0
 
 COCOTB_HDL_TIMEUNIT = 1ns
-COCOTB_HDL_TIMEPRECISION = 1ps
+COCOTB_HDL_TIMEPRECISION = 1fs
 
 DUT      = ptp_clock_cdc
 TOPLEVEL = $(DUT)
diff --git a/tb/ptp_clock_cdc/test_ptp_clock_cdc.py b/tb/ptp_clock_cdc/test_ptp_clock_cdc.py
