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Add example design for Alveo U55C
Signed-off-by: Alex Forencich <[email protected]>
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‎README.md‎

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@@ -21,6 +21,7 @@ Example designs are included for the following FPGA boards:
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* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)
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* Terasic DE10-Agilex (Intel Agilex F AGFB014R24B2E2V)
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* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
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* Xilinx Alveo U55C (Xilinx Virtex UltraScale+ XCU55C)
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* Xilinx Alveo U55N/Varium C1100 (Xilinx Virtex UltraScale+ XCU55N)
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* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
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* Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250)

‎example/Alveo/fpga/README.md‎

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@@ -8,6 +8,7 @@ The design implements the PCIe AXI lite master module, the PCIe AXI master modul
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* FPGA
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* AU50: xcu50-fsvh2104-2-e
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* AU55C: xcu55c-fsvh2892-2L-e
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* AU55N/C1100: xcu55n-fsvh2892-2L-e
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* AU200: xcu200-fsgd2104-2-e
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* AU250: xcu250-fsgd2104-2-e

‎example/Alveo/fpga/fpga_AU55C/Makefile‎

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# FPGA settings
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FPGA_PART = xcu55c-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga_au55.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/common/example_core_pcie_us.v
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SYN_FILES += rtl/common/example_core_pcie.v
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SYN_FILES += rtl/common/example_core.v
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SYN_FILES += rtl/common/axi_ram.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
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SYN_FILES += lib/pcie/rtl/pcie_msix.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/priority_encoder.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga_au55.xdc
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# IP
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IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%.mcs %.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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‎example/Alveo/fpga/fpga_AU55C/config.tcl‎

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set params [dict create]
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# Board info
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set board_vendor_id [expr 0x10ee]
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set board_device_id [expr 0x9037]
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# PCIe IDs
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set pcie_vendor_id [expr 0x1234]
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set pcie_device_id [expr 0x0001]
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set pcie_class_code [expr 0x058000]
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set pcie_revision_id [expr 0x00]
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set pcie_subsystem_vendor_id $board_vendor_id
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set pcie_subsystem_device_id $board_device_id
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# BAR sizes
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dict set params BAR0_APERTURE "24"
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dict set params BAR2_APERTURE "24"
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dict set params BAR4_APERTURE "16"
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# PCIe IP core settings
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set pcie [get_ips pcie4c_uscale_plus_0]
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# Internal interface settings
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dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
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# configure BAR settings
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proc configure_bar {pcie pf bar aperture} {
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set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
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for { set i 0 } { $i < [llength $size_list] } { incr i } {
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set scale [lindex $size_list $i]
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if {$aperture > 0 && $aperture < ($i+1)*10} {
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set size [expr 1 << $aperture - ($i*10)]
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puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
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set pcie_config [dict create]
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
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set_property -dict $pcie_config $pcie
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return
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}
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}
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puts "${pcie} PF${pf} BAR${bar}: disabled"
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set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
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}
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# Configure BARs
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configure_bar $pcie 0 0 [dict get $params BAR0_APERTURE]
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configure_bar $pcie 0 2 [dict get $params BAR2_APERTURE]
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configure_bar $pcie 0 4 [dict get $params BAR4_APERTURE]
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# PCIe IP core configuration
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set pcie_config [dict create]
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# PCIe IDs
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dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
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dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
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dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
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dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
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dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
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dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
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# MSI-X
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dict set pcie_config "CONFIG.pf0_msi_enabled" {false}
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dict set pcie_config "CONFIG.pf0_msix_enabled" {true}
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dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" {01F}
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dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_5:4}
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dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00000000}
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dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_5:4}
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dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00008000}
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dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External}
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set_property -dict $pcie_config $pcie
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# apply parameters to top-level
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set param_list {}
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dict for {name value} $params {
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lappend param_list $name=$value
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}
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# set_property generic $param_list [current_fileset]
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set_property generic $param_list [get_filesets sources_1]

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