hw/drivers: Add Ethernet support for STM32H7 devices

Author: m-gorecki

hw/bsp/nucleo-h723zg/src/hal_bsp.c

@@ -157,10 +157,11 @@ const struct stm32_eth_cfg os_bsp_eth0_cfg = {
 
     /*
      * PORTG
+     *   PG2  - ETH_RMII_RXER
      *   PG11 - ETH_RMII_TXEN
      *   PG13 - ETH_RMII_TXD0
      */
-    .sec_port_mask[6] = (1 << 11) | (1 << 13),
+    .sec_port_mask[6] = (1 << 2) | (1 << 11) | (1 << 13),
     .sec_phy_type = LAN_8742_RMII,
     .sec_phy_irq = -1
 };

hw/bsp/nucleo-h753zi/src/hal_bsp.c

@@ -131,6 +131,42 @@ const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = {
 };
 #endif
 
+#if MYNEWT_VAL(ETH_0)
+const struct stm32_eth_cfg os_bsp_eth0_cfg = {
+    /*
+     * PORTA
+     *   PA1 - ETH_RMII_REF_CLK
+     *   PA2 - ETH_RMII_MDIO
+     *   PA7 - ETH_RMII_CRS_DV
+     */
+    .sec_port_mask[0] = (1 << 1) | (1 << 2) | (1 << 7),
+
+    /*
+     * PORTB
+     *   PB13 - ETH_RMII_TXD1
+     */
+    .sec_port_mask[1] = (1 << 13),
+
+    /*
+     * PORTC
+     *   PC1 - ETH_RMII_MDC
+     *   PC4 - ETH_RMII_RXD0
+     *   PC5 - ETH_RMII_RXD1
+     */
+    .sec_port_mask[2] = (1 << 1) | (1 << 4) | (1 << 5),
+
+    /*
+     * PORTG
+     *   PG2  - ETH_RMII_RXER
+     *   PG11 - ETH_RMII_TXEN
+     *   PG13 - ETH_RMII_TXD0
+     */
+    .sec_port_mask[6] = (1 << 2) | (1 << 11) | (1 << 13),
+    .sec_phy_type = LAN_8742_RMII,
+    .sec_phy_irq = -1
+};
+#endif
+
 static const struct hal_bsp_mem_dump dump_cfg[] = {
     [0] = {
         .hbmd_start = _ram_start,

hw/drivers/lwip/stm32_eth/src/stm32_eth.c

@@ -31,6 +31,20 @@
 #include <bsp/stm32f7xx_hal_conf.h>
 #include <mcu/stm32f7_bsp.h>
 #endif
+#if MYNEWT_VAL(MCU_STM32H7)
+#include <bsp/stm32h7xx_hal_conf.h>
+#include <mcu/stm32h7_bsp.h>
+
+#define ETH_RX_BUF_SIZE           (ETH_MAX_PACKET_SIZE)
+#define PHY_BSR                   ((uint16_t)0x0001U)
+#define PHY_LINKED_STATUS         ((uint16_t)0x0004U)
+
+#define __HAL_RCC_ETH_CLK_ENABLE()       do { \
+        __HAL_RCC_ETH1MAC_CLK_ENABLE();   \
+        __HAL_RCC_ETH1TX_CLK_ENABLE();    \
+        __HAL_RCC_ETH1RX_CLK_ENABLE();    \
+} while (0)
+#endif
 
 #include <netif/etharp.h>
 #include <netif/ethernet.h>
@@ -338,10 +352,15 @@ stm32_lwip_init(struct netif *nif)
     ses->st_tx_cfg.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
     ses->st_tx_cfg.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
     ses->st_tx_cfg.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+
     /*
      * XXX pass all multicast traffic for now
      */
+#if MYNEWT_VAL(MCU_STM32H7)
+    ses->st_eth.Instance->MACPFR |= ETH_MACPFR_PM;
+#else
     ses->st_eth.Instance->MACFFR |= ETH_MULTICASTFRAMESFILTER_NONE;
+#endif
 
     if (HAL_ETH_Init(&ses->st_eth) == HAL_ERROR) {
         return ERR_IF;