diff --git a/core/src/main/scala/chisel3/internal/firrtl/Serializer.scala b/core/src/main/scala/chisel3/internal/firrtl/Serializer.scala
index c741b4c27fd..c30093272e6 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Serializer.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Serializer.scala
@@ -37,9 +37,10 @@ private[chisel3] object Serializer {
 
   /** Generate a legal FIRRTL name. */
   private def legalize(name: String): String = name match {
-    // If the name starts with a digit, then escape it with backticks.
+    // If the name starts with a digit, escape it with backticks.
     case _ if name.head.isDigit => s"`$name`"
-    case _                      => name
+    // Otherwise, use the common keyword legalization
+    case _ => fir.Keywords.legalize(name)
   }
 
   /** create a new line with the appropriate indent */
@@ -115,7 +116,7 @@ private[chisel3] object Serializer {
 
   private def serialize(arg: Arg, ctx: Component, info: SourceInfo)(implicit b: StringBuilder): Unit = arg match {
     case Node(id)  => serialize(getRef(id, info), ctx, info)
-    case Ref(name) => b ++= name
+    case Ref(name) => b ++= legalize(name)
     // We don't need to legalize Slot names, firtool can parse subfields starting with digits
     case Slot(imm, name) => serialize(imm, ctx, info); b += '.'; b ++= legalize(name)
     case OpaqueSlot(imm) => serialize(imm, ctx, info)
@@ -126,11 +127,11 @@ private[chisel3] object Serializer {
     case Index(imm, value) =>
       serialize(imm, ctx, info); b += '['; serialize(value, ctx, info); b += ']'
     case ModuleIO(mod, name) =>
-      if (mod eq ctx.id) { b ++= name }
-      else { b ++= getRef(mod, info).name; b += '.'; b ++= name }
+      if (mod eq ctx.id) { b ++= legalize(name) }
+      else { b ++= getRef(mod, info).name; b += '.'; b ++= legalize(name) }
     case ModuleCloneIO(mod, name) =>
       if (mod eq ctx.id) clonedModuleIOError(mod, name, info)
-      else { b ++= name }
+      else { b ++= legalize(name) }
     case u @ ULit(n, w) =>
       val width = w match {
         case UnknownWidth => u.minWidth
@@ -518,7 +519,7 @@ private[chisel3] object Serializer {
             b ++= "flip "
           case _ => ()
         }
-        b ++= legalize(getRef(elt, info).name); b ++= " : "
+        b ++= getRef(elt, info).name; b ++= " : "
         serializeType(elt, childClearDir, info, checkProbe, true, typeAliases)
       }
       if (!t._isOpaqueType) {
diff --git a/firrtl/src/main/scala/firrtl/ir/Keywords.scala b/firrtl/src/main/scala/firrtl/ir/Keywords.scala
new file mode 100644
index 00000000000..6cc640f115a
--- /dev/null
+++ b/firrtl/src/main/scala/firrtl/ir/Keywords.scala
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package firrtl.ir
+
+/** Object containing the set of FIRRTL keywords that need to be escaped when used as identifiers.
+  *
+  * This includes keywords from the FIRRTL specification as well as additional keywords recognized
+  * by the CIRCT FIRRTL parser (from FIRTokenKinds.def).
+  */
+object Keywords {
+
+  /** Set of FIRRTL keywords that need to be escaped when used as identifiers. */
+  val keywords: Set[String] = Set(
+    // Top-level keywords
+    "FIRRTL",
+    "version",
+    "circuit",
+    "public",
+    "module",
+    "extmodule",
+    "layer",
+    "formal",
+    "type",
+    // Port and parameter keywords
+    "input",
+    "output",
+    "parameter",
+    "defname",
+    // Layer keywords
+    "bind",
+    "inline",
+    "enablelayer",
+    "knownlayer",
+    "layerblock",
+    // Statement keywords
+    "node",
+    "wire",
+    "reg",
+    "regreset",
+    "inst",
+    "of",
+    "mem",
+    "skip",
+    // Memory keywords
+    "data-type",
+    "depth",
+    "read-latency",
+    "write-latency",
+    "read-under-write",
+    "reader",
+    "writer",
+    "readwriter",
+    "old",
+    "new",
+    "undefined",
+    // Connect-like keywords
+    "connect",
+    "invalidate",
+    "attach",
+    "define",
+    "propassign",
+    // Conditional keywords
+    "when",
+    "else",
+    "match",
+    // Command keywords
+    "stop",
+    "force",
+    "force_initial",
+    "release",
+    "release_initial",
+    "printf",
+    "fprintf",
+    "fflush",
+    "assert",
+    "assume",
+    "cover",
+    "intrinsic",
+    // Type keywords
+    "const",
+    "Clock",
+    "Reset",
+    "AsyncReset",
+    "UInt",
+    "SInt",
+    "Analog",
+    "Probe",
+    "RWProbe",
+    "flip",
+    "Unknown",
+    "Bool",
+    "Fixed",
+    "AnyRef",
+    "Path",
+    "Inst",
+    "Domain",
+    "Double",
+    "String",
+    "Integer",
+    "List",
+    // Expression keywords
+    "mux",
+    "read",
+    "probe",
+    "rwprobe",
+    // PrimOp keywords
+    "asUInt",
+    "asSInt",
+    "asClock",
+    "asAsyncReset",
+    "asReset",
+    "cvt",
+    "neg",
+    "not",
+    "andr",
+    "orr",
+    "xorr",
+    "add",
+    "sub",
+    "mul",
+    "div",
+    "rem",
+    "lt",
+    "leq",
+    "gt",
+    "geq",
+    "eq",
+    "neq",
+    "dshl",
+    "dshr",
+    "dshlw",
+    "and",
+    "or",
+    "xor",
+    "cat",
+    "pad",
+    "shl",
+    "shr",
+    "head",
+    "tail",
+    "bits",
+    "integer_add",
+    "integer_mul",
+    "integer_shr",
+    "integer_shl",
+    "list_concat",
+    "tagExtract",
+    // Additional CIRCT keywords not in spec (from FIRTokenKinds.def)
+    "case",
+    "class",
+    "cmem",
+    "contract",
+    "declgroup",
+    "domain_define",
+    "domains",
+    "extclass",
+    "false",
+    "group",
+    "infer",
+    "instchoice",
+    "intmodule",
+    "invalid",
+    "is",
+    "mport",
+    "object",
+    "option",
+    "rdwr",
+    "ref",
+    "requires",
+    "reset",
+    "simulation",
+    "smem",
+    "symbolic",
+    "true",
+    "with",
+    "write",
+    "unsafe_domain_cast"
+  )
+
+  /** Legalize a name by escaping it with backticks if it's a FIRRTL keyword.
+    * 
+    * @param name the name to legalize
+    * @return the legalized name (with backticks if it's a keyword)
+    */
+  def legalize(name: String): String = {
+    if (keywords.contains(name)) s"`$name`" else name
+  }
+}
diff --git a/firrtl/src/main/scala/firrtl/ir/Serializer.scala b/firrtl/src/main/scala/firrtl/ir/Serializer.scala
index ce5053f1ffd..b5485cc128c 100644
--- a/firrtl/src/main/scala/firrtl/ir/Serializer.scala
+++ b/firrtl/src/main/scala/firrtl/ir/Serializer.scala
@@ -89,9 +89,10 @@ object Serializer {
 
   /** Generate a legal FIRRTL name. */
   private def legalize(name: String): String = name match {
-    // If the name starts with a digit, then escape it with backticks.
+    // If the name starts with a digit, escape it with backticks.
     case _ if name.head.isDigit => legalizedNames.getOrElseUpdate(name, s"`$name`")
-    case _                      => name
+    // Otherwise, use the common keyword legalization
+    case _ => legalizedNames.getOrElseUpdate(name, Keywords.legalize(name))
   }
 
   private def s(str: StringLit)(implicit b: StringBuilder, indent: Int): Unit = b ++= str.serialize
diff --git a/firrtl/src/test/scala/firrtlTests/SerializerSpec.scala b/firrtl/src/test/scala/firrtlTests/SerializerSpec.scala
index cc91bcb4547..f92bd34ac3b 100644
--- a/firrtl/src/test/scala/firrtlTests/SerializerSpec.scala
+++ b/firrtl/src/test/scala/firrtlTests/SerializerSpec.scala
@@ -428,6 +428,40 @@ class SerializerSpec extends AnyFlatSpec with Matchers {
       )
     ) should include("""assert(`42_clock`, `42_predicate`, `42_enable`, "message %d", `42_arg`) : `42_label`""")
     info("fprintf okay!")
+  }
+
+  it should "escape FIRRTL keywords when used as identifiers" in {
+    info("type keywords okay!")
+    Seq("UInt", "Clock", "Reset").foreach { keyword =>
+      Serializer.serialize(Port(NoInfo, keyword, Input, UIntType(IntWidth(1)), Seq.empty)) should include(
+        s"input `$keyword`"
+      )
+    }
+
+    info("statement keywords okay!")
+    Seq("wire", "reg", "node", "skip", "when", "inst").foreach { keyword =>
+      Serializer.serialize(DefWire(NoInfo, keyword, UIntType(IntWidth(1)))) should include(s"wire `$keyword`")
+    }
+
+    info("primop keywords okay!")
+    Seq("add", "sub", "mul", "and", "or", "xor", "mux").foreach { keyword =>
+      Serializer.serialize(DefWire(NoInfo, keyword, UIntType(IntWidth(1)))) should include(s"wire `$keyword`")
+    }
+
+    info("module keywords okay!")
+    Seq("module", "circuit", "input", "output").foreach { keyword =>
+      Serializer.serialize(DefWire(NoInfo, keyword, UIntType(IntWidth(1)))) should include(s"wire `$keyword`")
+    }
+
+    info("connect keywords okay!")
+    Seq("connect", "invalidate", "attach").foreach { keyword =>
+      Serializer.serialize(DefWire(NoInfo, keyword, UIntType(IntWidth(1)))) should include(s"wire `$keyword`")
+    }
+
+    info("command keywords okay!")
+    Seq("printf", "assert", "assume", "cover").foreach { keyword =>
+      Serializer.serialize(DefWire(NoInfo, keyword, UIntType(IntWidth(1)))) should include(s"wire `$keyword`")
+    }
     Serializer.serialize(
       Fprint(
         NoInfo,
diff --git a/lit/tests/Converter/Circuit.sc b/lit/tests/Converter/Circuit.sc
index 07a507ce719..8c499124d98 100644
--- a/lit/tests/Converter/Circuit.sc
+++ b/lit/tests/Converter/Circuit.sc
@@ -17,7 +17,7 @@ class FooBlackbox extends BlackBox {
 
 // CHECK: public module FooModule :
 // CHECK-NEXT: input clock : Clock
-// CHECK-NEXT: input reset : UInt<1>
+// CHECK-NEXT: input `reset` : UInt<1>
 // CHECK-NEXT: output o : UInt<1>
 class FooModule extends Module {
   val o = IO(Output(Bool()))
diff --git a/lit/tests/Converter/Debug.sc b/lit/tests/Converter/Debug.sc
index 696414a54bf..0c943706915 100644
--- a/lit/tests/Converter/Debug.sc
+++ b/lit/tests/Converter/Debug.sc
@@ -32,7 +32,7 @@ class Verf extends Module {
 println(circt.stage.ChiselStage.emitCHIRRTL(new Verf))
 
 // Following test ported from ProbeSpec.scala in chisel test suite
-// CHECK-LABEL: circuit Probe :
+// CHECK-LABEL: circuit `Probe` :
 class Probe extends Module {
   val x = IO(Input(Bool()))
   val y = IO(Output(Bool()))
diff --git a/lit/tests/Converter/Module.sc b/lit/tests/Converter/Module.sc
index 5631e497912..3a085fe0e1e 100644
--- a/lit/tests/Converter/Module.sc
+++ b/lit/tests/Converter/Module.sc
@@ -7,7 +7,7 @@ import chisel3.util.SRAM
 
 // CHECK-LABEL: public module Attach :
 // CHECK-NEXT:   input clock : Clock
-// CHECK-NEXT:   input reset : UInt<1>
+// CHECK-NEXT:   input `reset` : UInt<1>
 class Attach extends Module {
   // CHECK-NEXT: output o : Analog<1>
   val o = IO(Analog(1.W))
@@ -22,7 +22,7 @@ println(circt.stage.ChiselStage.emitCHIRRTL(new Attach))
 
 // CHECK-LABEL: public module Cond :
 // CHECK-NEXT:   input clock : Clock
-// CHECK-NEXT:   input reset : UInt<1>
+// CHECK-NEXT:   input `reset` : UInt<1>
 class Cond extends Module {
   // CHECK-NEXT: input i : UInt<2>
   val i = IO(Input(UInt(2.W)))
@@ -51,7 +51,7 @@ println(circt.stage.ChiselStage.emitCHIRRTL(new Cond))
 
 // CHECK-LABEL: public module Mem :
 // CHECK-NEXT:   input clock : Clock
-// CHECK-NEXT:   input reset : UInt<1>
+// CHECK-NEXT:   input `reset` : UInt<1>
 class Mem extends Module {
   // CHECK: output r : { flip enable : UInt<1>,
   val r = IO(new Bundle {
@@ -70,14 +70,14 @@ class Mem extends Module {
     val data = Input(UInt(32.W))
   })
 
-  // CHECK: smem mem : UInt<32>[1024]
+  // CHECK: smem `mem` : UInt<32>[1024]
   val mem = SyncReadMem(1024, UInt(32.W))
 
   // CHECK: invalidate r.data
   r.data := DontCare
   // CHECK: when r.enable :
   when (r.enable) {
-    // CHECK-NEXT: infer mport wrPort = mem[r.address], clock
+    // CHECK-NEXT: infer mport wrPort = `mem`[r.address], clock
     val wrPort = mem(r.address)
     // CHECK-NEXT: connect r.data, wrPort
     r.data := wrPort
@@ -87,7 +87,7 @@ class Mem extends Module {
 
   // CHECK: when w.enable :
   when (w.enable) {
-    // CHECK-NEXT: infer mport wrPort_1 = mem[w.address], clock
+    // CHECK-NEXT: infer mport wrPort_1 = `mem`[w.address], clock
     val wrPort = mem(w.address)
     // CHECK-NEXT: connect wrPort_1, w.data
     wrPort := w.data
@@ -98,85 +98,85 @@ println(circt.stage.ChiselStage.emitCHIRRTL(new Mem))
 
 // CHECK-LABEL: public module Sram :
 // CHECK-NEXT:   input clock : Clock
-// CHECK-NEXT:   input reset : UInt<1>
+// CHECK-NEXT:   input `reset` : UInt<1>
 class Sram extends Module {
-  // CHECK:      wire mem
+  // CHECK:      wire `mem`
   // CHECK:      mem mem_sram
-  // CHECK:      connect mem_sram.R0.addr, mem.readPorts[0].address
+  // CHECK:      connect mem_sram.R0.addr, `mem`.readPorts[0].address
   // CHECK-NEXT: connect mem_sram.R0.clk, clock
-  // CHECK-NEXT: connect mem.readPorts[0].data, mem_sram.R0.data
-  // CHECK-NEXT: connect mem_sram.R0.en, mem.readPorts[0].enable
-  // CHECK-NEXT: connect mem_sram.R1.addr, mem.readPorts[1].address
+  // CHECK-NEXT: connect `mem`.readPorts[0].data, mem_sram.R0.data
+  // CHECK-NEXT: connect mem_sram.R0.en, `mem`.readPorts[0].enable
+  // CHECK-NEXT: connect mem_sram.R1.addr, `mem`.readPorts[1].address
   // CHECK-NEXT: connect mem_sram.R1.clk, clock
-  // CHECK-NEXT: connect mem.readPorts[1].data, mem_sram.R1.data
-  // CHECK-NEXT: connect mem_sram.R1.en, mem.readPorts[1].enable
-  // CHECK-NEXT: connect mem_sram.W0.addr, mem.writePorts[0].address
+  // CHECK-NEXT: connect `mem`.readPorts[1].data, mem_sram.R1.data
+  // CHECK-NEXT: connect mem_sram.R1.en, `mem`.readPorts[1].enable
+  // CHECK-NEXT: connect mem_sram.W0.addr, `mem`.writePorts[0].address
   // CHECK-NEXT: connect mem_sram.W0.clk, clock
-  // CHECK-NEXT: connect mem_sram.W0.data, mem.writePorts[0].data
-  // CHECK-NEXT: connect mem_sram.W0.en, mem.writePorts[0].enable
+  // CHECK-NEXT: connect mem_sram.W0.data, `mem`.writePorts[0].data
+  // CHECK-NEXT: connect mem_sram.W0.en, `mem`.writePorts[0].enable
   // CHECK-NEXT: connect mem_sram.W0.mask, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem_sram.W1.addr, mem.writePorts[1].address
+  // CHECK-NEXT: connect mem_sram.W1.addr, `mem`.writePorts[1].address
   // CHECK-NEXT: connect mem_sram.W1.clk, clock
-  // CHECK-NEXT: connect mem_sram.W1.data, mem.writePorts[1].data
-  // CHECK-NEXT: connect mem_sram.W1.en, mem.writePorts[1].enable
+  // CHECK-NEXT: connect mem_sram.W1.data, `mem`.writePorts[1].data
+  // CHECK-NEXT: connect mem_sram.W1.en, `mem`.writePorts[1].enable
   // CHECK-NEXT: connect mem_sram.W1.mask, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem_sram.RW0.addr, mem.readwritePorts[0].address
+  // CHECK-NEXT: connect mem_sram.RW0.addr, `mem`.readwritePorts[0].address
   // CHECK-NEXT: connect mem_sram.RW0.clk, clock
-  // CHECK-NEXT: connect mem_sram.RW0.en, mem.readwritePorts[0].enable
-  // CHECK-NEXT: connect mem.readwritePorts[0].readData, mem_sram.RW0.rdata
-  // CHECK-NEXT: connect mem_sram.RW0.wdata, mem.readwritePorts[0].writeData
-  // CHECK-NEXT: connect mem_sram.RW0.wmode, mem.readwritePorts[0].isWrite
+  // CHECK-NEXT: connect mem_sram.RW0.en, `mem`.readwritePorts[0].enable
+  // CHECK-NEXT: connect `mem`.readwritePorts[0].readData, mem_sram.RW0.rdata
+  // CHECK-NEXT: connect mem_sram.RW0.wdata, `mem`.readwritePorts[0].writeData
+  // CHECK-NEXT: connect mem_sram.RW0.wmode, `mem`.readwritePorts[0].isWrite
   // CHECK-NEXT: connect mem_sram.RW0.wmask, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem_sram.RW1.addr, mem.readwritePorts[1].address
+  // CHECK-NEXT: connect mem_sram.RW1.addr, `mem`.readwritePorts[1].address
   // CHECK-NEXT: connect mem_sram.RW1.clk, clock
-  // CHECK-NEXT: connect mem_sram.RW1.en, mem.readwritePorts[1].enable
-  // CHECK-NEXT: connect mem.readwritePorts[1].readData, mem_sram.RW1.rdata
-  // CHECK-NEXT: connect mem_sram.RW1.wdata, mem.readwritePorts[1].writeData
-  // CHECK-NEXT: connect mem_sram.RW1.wmode, mem.readwritePorts[1].isWrite
+  // CHECK-NEXT: connect mem_sram.RW1.en, `mem`.readwritePorts[1].enable
+  // CHECK-NEXT: connect `mem`.readwritePorts[1].readData, mem_sram.RW1.rdata
+  // CHECK-NEXT: connect mem_sram.RW1.wdata, `mem`.readwritePorts[1].writeData
+  // CHECK-NEXT: connect mem_sram.RW1.wmode, `mem`.readwritePorts[1].isWrite
   // CHECK-NEXT: connect mem_sram.RW1.wmask, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem_sram.RW2.addr, mem.readwritePorts[2].address
+  // CHECK-NEXT: connect mem_sram.RW2.addr, `mem`.readwritePorts[2].address
   // CHECK-NEXT: connect mem_sram.RW2.clk, clock
-  // CHECK-NEXT: connect mem_sram.RW2.en, mem.readwritePorts[2].enable
-  // CHECK-NEXT: connect mem.readwritePorts[2].readData, mem_sram.RW2.rdata
-  // CHECK-NEXT: connect mem_sram.RW2.wdata, mem.readwritePorts[2].writeData
-  // CHECK-NEXT: connect mem_sram.RW2.wmode, mem.readwritePorts[2].isWrite
+  // CHECK-NEXT: connect mem_sram.RW2.en, `mem`.readwritePorts[2].enable
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].readData, mem_sram.RW2.rdata
+  // CHECK-NEXT: connect mem_sram.RW2.wdata, `mem`.readwritePorts[2].writeData
+  // CHECK-NEXT: connect mem_sram.RW2.wmode, `mem`.readwritePorts[2].isWrite
   // CHECK-NEXT: connect mem_sram.RW2.wmask, UInt<1>(0h1)
   val mem = SRAM(1024, UInt(8.W), 2, 2, 3)
 
-  // CHECK-NEXT: connect mem.readPorts[0].address, UInt<7>(0h64)
-  // CHECK-NEXT: connect mem.readPorts[0].enable, UInt<1>(0h1)
+  // CHECK-NEXT: connect `mem`.readPorts[0].address, UInt<7>(0h64)
+  // CHECK-NEXT: connect `mem`.readPorts[0].enable, UInt<1>(0h1)
   mem.readPorts(0).address := 100.U
   mem.readPorts(0).enable := true.B
 
   // CHECK-NEXT: wire foo : UInt<8>
-  // CHECK-NEXT: connect foo, mem.readPorts[0].data
+  // CHECK-NEXT: connect foo, `mem`.readPorts[0].data
   val foo = WireInit(UInt(8.W), mem.readPorts(0).data)
 
-  // CHECK-NEXT: connect mem.writePorts[1].address, UInt<3>(0h5)
-  // CHECK-NEXT: connect mem.writePorts[1].enable, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem.writePorts[1].data, UInt<4>(0hc)
+  // CHECK-NEXT: connect `mem`.writePorts[1].address, UInt<3>(0h5)
+  // CHECK-NEXT: connect `mem`.writePorts[1].enable, UInt<1>(0h1)
+  // CHECK-NEXT: connect `mem`.writePorts[1].data, UInt<4>(0hc)
   mem.writePorts(1).address := 5.U
   mem.writePorts(1).enable := true.B
   mem.writePorts(1).data := 12.U
 
-  // CHECK-NEXT: connect mem.readwritePorts[2].address, UInt<3>(0h5)
-  // CHECK-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem.readwritePorts[2].writeData, UInt<7>(0h64)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].address, UInt<3>(0h5)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].enable, UInt<1>(0h1)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].isWrite, UInt<1>(0h1)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].writeData, UInt<7>(0h64)
   mem.readwritePorts(2).address := 5.U
   mem.readwritePorts(2).enable := true.B
   mem.readwritePorts(2).isWrite := true.B
   mem.readwritePorts(2).writeData := 100.U
 
-  // CHECK-NEXT: connect mem.readwritePorts[2].address, UInt<3>(0h5)
-  // CHECK-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(0h1)
-  // CHECK-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(0h0)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].address, UInt<3>(0h5)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].enable, UInt<1>(0h1)
+  // CHECK-NEXT: connect `mem`.readwritePorts[2].isWrite, UInt<1>(0h0)
   mem.readwritePorts(2).address := 5.U
   mem.readwritePorts(2).enable := true.B
   mem.readwritePorts(2).isWrite := false.B
 
   // CHECK-NEXT: wire bar : UInt<8>
-  // CHECK-NEXT: connect bar, mem.readwritePorts[2].readData
+  // CHECK-NEXT: connect bar, `mem`.readwritePorts[2].readData
   val bar = WireInit(UInt(8.W), mem.readwritePorts(2).readData)
 }
 
@@ -184,16 +184,16 @@ println(circt.stage.ChiselStage.emitCHIRRTL(new Sram))
 
 // CHECK-LABEL: public module WireAndReg :
 // CHECK-NEXT:   input clock : Clock
-// CHECK-NEXT:   input reset : UInt<1>
+// CHECK-NEXT:   input `reset` : UInt<1>
 class WireAndReg extends Module {
   // CHECK-NEXT: input r : UInt<1>
   val r = IO(Input(Bool()))
   // CHECK-NEXT: output o : UInt<2>
   val o = IO(Output(UInt(2.W)))
 
-  // CHECK: regreset o_next : UInt<1>, clock, reset, UInt<1>(0h0)
+  // CHECK: regreset o_next : UInt<1>, clock, `reset`, UInt<1>(0h0)
   val o_next = RegInit(false.B)
-  // CHECK: reg flip : UInt<1>, clock
+  // CHECK: reg `flip` : UInt<1>, clock
   val flip = Reg(Bool())
   // CHECK: wire magic : SInt<8>
   val magic = Wire(SInt(8.W))
@@ -202,9 +202,9 @@ class WireAndReg extends Module {
   // CHECK-NEXT: and(o_next
   // CHECK-NEXT: connect o
   o := o_next && magic(7)
-  // CHECK:      connect o_next, flip
+  // CHECK:      connect o_next, `flip`
   o_next := flip
-  // CHECK:      xor(flip, r)
+  // CHECK:      xor(`flip`, r)
   flip := flip ^ r
   // CHECK:      connect magic, SInt<7>(-0h2a)
   magic := -42.S
diff --git a/lit/tests/SmokeTest.sc b/lit/tests/SmokeTest.sc
index d85c80a09fd..68c17308ff3 100644
--- a/lit/tests/SmokeTest.sc
+++ b/lit/tests/SmokeTest.sc
@@ -11,7 +11,7 @@ class FooBundle extends Bundle {
 // FIRRTL-LABEL: circuit FooModule :
 // FIRRTL:         public module FooModule :
 // FIRRTL-NEXT:      input clock : Clock
-// FIRRTL-NEXT:      input reset : UInt<1>
+// FIRRTL-NEXT:      input `reset` : UInt<1>
 // FIRRTL-NEXT:      output io : { flip foo : UInt<3>}
 // FIRRTL:           skip
 
diff --git a/src/test/scala-2/chiselTests/BoringUtilsTapSpec.scala b/src/test/scala-2/chiselTests/BoringUtilsTapSpec.scala
index 42d03e6c536..ba620030286 100644
--- a/src/test/scala-2/chiselTests/BoringUtilsTapSpec.scala
+++ b/src/test/scala-2/chiselTests/BoringUtilsTapSpec.scala
@@ -642,7 +642,7 @@ class BoringUtilsTapSpec extends AnyFlatSpec with Matchers with FileCheck {
            |CHECK:         define widgetProbes_p_bore_1 = hier.widgetProbes_p_bore_1
            |CHECK-LABEL: public module Dut :
            |CHECK:         input clock : Clock
-           |CHECK:         input reset : UInt<1>
+           |CHECK:         input `reset` : UInt<1>
            |CHECK:         output widgetProbes_0 : RWProbe<UInt<32>>
            |CHECK:         output widgetProbes_1 : RWProbe<UInt<32>>
            |CHECK:         inst hier of ArbitrarilyDeepHierarchy
@@ -769,7 +769,7 @@ class BoringUtilsTapSpec extends AnyFlatSpec with Matchers with FileCheck {
       .fileCheck()(
         """|CHECK-LABEL: module Widget :
            |CHECK:         input clock : Clock
-           |CHECK:         input reset : Reset
+           |CHECK:         input `reset` : Reset
            |CHECK:         input in : UInt<32>
            |CHECK:         output out : UInt<32>
            |CHECK:         node _out_T = not(in)
@@ -816,7 +816,7 @@ class BoringUtilsTapSpec extends AnyFlatSpec with Matchers with FileCheck {
       .fileCheck()(
         """|CHECK-LABEL: module Widget :
            |CHECK:         input clock : Clock
-           |CHECK:         input reset : Reset
+           |CHECK:         input `reset` : Reset
            |CHECK:         input in : UInt<32>
            |CHECK:         output out : UInt<32>
            |CHECK:         node _out_T = not(in)
@@ -907,7 +907,7 @@ class BoringUtilsTapSpec extends AnyFlatSpec with Matchers with FileCheck {
         """|CHECK-LABEL: module Foo :
            |CHECK:         wire a : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
            |CHECK:         wire b : { ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
-           |CHECK:         connect b.bits, a.bits
+           |CHECK:         connect b.`bits`, a.`bits`
            |CHECK:         connect b.valid, a.valid
            |CHECK:         connect b.ready, a.ready
            |""".stripMargin
diff --git a/src/test/scala-2/chiselTests/Direction.scala b/src/test/scala-2/chiselTests/Direction.scala
index bedd906ca65..5e6862d4c87 100644
--- a/src/test/scala-2/chiselTests/Direction.scala
+++ b/src/test/scala-2/chiselTests/Direction.scala
@@ -487,7 +487,7 @@ class DirectionSpec extends AnyPropSpec with Matchers {
       )
     )
     assert(emitted.contains("connect io.consumer, io.producer"))
-    assert(emitted.contains("connect io.monitor.bits, io.driver.bits"))
+    assert(emitted.contains("connect io.monitor.`bits`, io.driver.`bits`"))
     assert(emitted.contains("connect io.monitor.valid, io.driver.valid"))
     assert(emitted.contains("connect io.monitor.ready, io.driver.ready"))
   }
diff --git a/src/test/scala-2/chiselTests/DisableSpec.scala b/src/test/scala-2/chiselTests/DisableSpec.scala
index d908b1029a2..347ea728730 100644
--- a/src/test/scala-2/chiselTests/DisableSpec.scala
+++ b/src/test/scala-2/chiselTests/DisableSpec.scala
@@ -33,7 +33,7 @@ class DisableSpec extends AnyFlatSpec with Matchers {
       val doDisable = Module.disableOption
     })
     chirrtl should include("module Top :")
-    chirrtl should include("node doDisable_has_been_reset = intrinsic(circt_has_been_reset : UInt<1>, clock, reset)")
+    chirrtl should include("node doDisable_has_been_reset = intrinsic(circt_has_been_reset : UInt<1>, clock, `reset`)")
     chirrtl should include("node doDisable = eq(doDisable_has_been_reset, UInt<1>(0h0))")
   }
 
diff --git a/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala b/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
index 179e7fc889b..4069fefb95a 100644
--- a/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
+++ b/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
@@ -331,7 +331,7 @@ class FixedIOModuleSpec extends AnyFlatSpec with Matchers with FileCheck {
       .fileCheck()(
         """| CHECK: module Foo :
            | CHECK:   input clock : Clock
-           | CHECK:   input reset : UInt<1>
+           | CHECK:   input `reset` : UInt<1>
            | CHECK:   output io : UInt<8>
            |""".stripMargin
       )
diff --git a/src/test/scala-2/chiselTests/Mem.scala b/src/test/scala-2/chiselTests/Mem.scala
index ea52c5e8bf9..12e9f4fb5d8 100644
--- a/src/test/scala-2/chiselTests/Mem.scala
+++ b/src/test/scala-2/chiselTests/Mem.scala
@@ -371,7 +371,7 @@ class MemorySpec extends AnyPropSpec with Matchers with ChiselSim {
   property("SyncReadMems should be able to have an explicit number of read-write ports") {
     // Check if there is exactly one MemReadWrite port (TODO: extend to Nr/Nw?)
     val chirrtl = ChiselStage.emitCHIRRTL(new MemReadWriteTester)
-    chirrtl should include(s"rdwr mport rdata = mem[_rdata_T_1], clock")
+    chirrtl should include(s"rdwr mport rdata = `mem`[_rdata_T_1], clock")
 
     // Check read/write logic
     simulate(new MemReadWriteTester)(RunUntilFinished(7))
@@ -380,7 +380,7 @@ class MemorySpec extends AnyPropSpec with Matchers with ChiselSim {
   property("SyncReadMem masked read-writes should work") {
     // Check if there is exactly one MemReadWrite port (TODO: extend to Nr/Nw?)
     val chirrtl = ChiselStage.emitCHIRRTL(new MemMaskedReadWriteTester)
-    chirrtl should include(s"rdwr mport rdata = mem[_rdata_T_1], clock")
+    chirrtl should include(s"rdwr mport rdata = `mem`[_rdata_T_1], clock")
 
     // Check read/write logic
     simulate(new MemMaskedReadWriteTester)(RunUntilFinished(12))
@@ -390,9 +390,9 @@ class MemorySpec extends AnyPropSpec with Matchers with ChiselSim {
     val addrWidth = 65
     val size = BigInt(1) << addrWidth
     val smem = ChiselStage.emitCHIRRTL(new HugeSMemTester(size))
-    smem should include(s"smem mem : UInt<8>[$size]")
+    smem should include(s"smem `mem` : UInt<8>[$size]")
     val cmem = ChiselStage.emitCHIRRTL(new HugeCMemTester(size))
-    cmem should include(s"cmem mem : UInt<8>[$size]")
+    cmem should include(s"cmem `mem` : UInt<8>[$size]")
   }
 
   property("Implicit conversions with Mem indices should work") {
@@ -493,24 +493,24 @@ class SRAMSpec extends AnyFunSpec with Matchers {
         // Check that the chirrtl ports actually exist and the signals
         // are properly connected
         for (rd <- 0 until numRD) {
-          chirrtl should include(s"connect mem_sram.R$rd.addr, mem.readPorts[$rd].address")
-          chirrtl should include(s"connect mem.readPorts[$rd].data, mem_sram.R$rd.data")
-          chirrtl should include(s"connect mem_sram.R$rd.en, mem.readPorts[$rd].enable")
+          chirrtl should include(s"connect mem_sram.R$rd.addr, `mem`.readPorts[$rd].address")
+          chirrtl should include(s"connect `mem`.readPorts[$rd].data, mem_sram.R$rd.data")
+          chirrtl should include(s"connect mem_sram.R$rd.en, `mem`.readPorts[$rd].enable")
         }
 
         for (wr <- 0 until numWR) {
-          chirrtl should include(s"connect mem_sram.W$wr.addr, mem.writePorts[$wr].address")
-          chirrtl should include(s"connect mem_sram.W$wr.data, mem.writePorts[$wr].data")
-          chirrtl should include(s"connect mem_sram.W$wr.en, mem.writePorts[$wr].enable")
+          chirrtl should include(s"connect mem_sram.W$wr.addr, `mem`.writePorts[$wr].address")
+          chirrtl should include(s"connect mem_sram.W$wr.data, `mem`.writePorts[$wr].data")
+          chirrtl should include(s"connect mem_sram.W$wr.en, `mem`.writePorts[$wr].enable")
           chirrtl should include(s"connect mem_sram.W$wr.mask, UInt<1>(0h1)")
         }
 
         for (rw <- 0 until numRW) {
-          chirrtl should include(s"connect mem_sram.RW$rw.addr, mem.readwritePorts[$rw].address")
-          chirrtl should include(s"connect mem_sram.RW$rw.en, mem.readwritePorts[$rw].enable")
-          chirrtl should include(s"connect mem.readwritePorts[$rw].readData, mem_sram.RW$rw.rdata")
-          chirrtl should include(s"connect mem_sram.RW$rw.wdata, mem.readwritePorts[$rw].writeData")
-          chirrtl should include(s"connect mem_sram.RW$rw.wmode, mem.readwritePorts[$rw].isWrite")
+          chirrtl should include(s"connect mem_sram.RW$rw.addr, `mem`.readwritePorts[$rw].address")
+          chirrtl should include(s"connect mem_sram.RW$rw.en, `mem`.readwritePorts[$rw].enable")
+          chirrtl should include(s"connect `mem`.readwritePorts[$rw].readData, mem_sram.RW$rw.rdata")
+          chirrtl should include(s"connect mem_sram.RW$rw.wdata, `mem`.readwritePorts[$rw].writeData")
+          chirrtl should include(s"connect mem_sram.RW$rw.wmode, `mem`.readwritePorts[$rw].isWrite")
           chirrtl should include(s"connect mem_sram.RW$rw.wmask, UInt<1>(0h1)")
 
         }
@@ -540,8 +540,8 @@ class SRAMSpec extends AnyFunSpec with Matchers {
       )
 
       for (i <- 0 until 3) {
-        chirrtl should include(s"connect mem_sram.W0.mask[$i], mem.writePorts[0].mask[$i]")
-        chirrtl should include(s"connect mem_sram.RW0.wmask[$i], mem.readwritePorts[0].mask[$i]")
+        chirrtl should include(s"connect mem_sram.W0.mask[$i], `mem`.writePorts[0].mask[$i]")
+        chirrtl should include(s"connect mem_sram.RW0.wmask[$i], `mem`.readwritePorts[0].mask[$i]")
       }
     }
 
diff --git a/src/test/scala-2/chiselTests/ModuleChoiceSpec.scala b/src/test/scala-2/chiselTests/ModuleChoiceSpec.scala
index 438c91c4ac5..321ce2ea4a3 100644
--- a/src/test/scala-2/chiselTests/ModuleChoiceSpec.scala
+++ b/src/test/scala-2/chiselTests/ModuleChoiceSpec.scala
@@ -50,7 +50,7 @@ class ModuleChoiceSpec extends AnyFlatSpec with Matchers with FileCheck {
         """|CHECK: option Platform :
            |CHECK-NEXT: FPGA
            |CHECK-NEXT: ASIC
-           |CHECK: instchoice inst of VerifTarget, Platform :
+           |CHECK: instchoice `inst` of VerifTarget, Platform :
            |CHECK-NEXT: FPGA => FPGATarget
            |CHECK-NEXT: ASIC => ASICTarget""".stripMargin
       )
@@ -69,7 +69,7 @@ class ModuleChoiceSpec extends AnyFlatSpec with Matchers with FileCheck {
         """|CHECK: option Platform :
            |CHECK-NEXT: FPGA
            |CHECK-NEXT: ASIC
-           |CHECK: instchoice inst of VerifTarget, Platform :
+           |CHECK: instchoice `inst` of VerifTarget, Platform :
            |CHECK-NEXT: FPGA => FPGATarget
            |CHECK-NEXT: ASIC => ASICTarget""".stripMargin
       )
@@ -115,7 +115,7 @@ class ModuleChoiceSpec extends AnyFlatSpec with Matchers with FileCheck {
       .fileCheck()(
         """|CHECK: option Platform :
            |CHECK-NEXT: FPGA
-           |CHECK: instchoice inst of VerifTarget, Platform :
+           |CHECK: instchoice `inst` of VerifTarget, Platform :
            |CHECK-NEXT: FPGA => FPGATarget""".stripMargin
       )
   }
diff --git a/src/test/scala-2/chiselTests/Vec.scala b/src/test/scala-2/chiselTests/Vec.scala
index 3bd6f619e69..0d091280e44 100644
--- a/src/test/scala-2/chiselTests/Vec.scala
+++ b/src/test/scala-2/chiselTests/Vec.scala
@@ -407,7 +407,7 @@ class VecSpec extends AnyPropSpec with Matchers with LogUtils with FileCheck {
     for (gen <- List(new EmptyBundle, new EmptyRecord)) {
       val chirrtl = ChiselStage.emitCHIRRTL(new MyModule(gen))
       chirrtl should include("input in : { }")
-      chirrtl should include("regreset reg : { }[4]")
+      chirrtl should include("regreset `reg` : { }[4]")
     }
   }
 
@@ -517,7 +517,7 @@ class VecSpec extends AnyPropSpec with Matchers with LogUtils with FileCheck {
     ChiselStage
       .emitCHIRRTL(new Top)
       .fileCheck()(
-        """|CHECK: read mport port = mem[_port_WIRE], clock
+        """|CHECK: read mport port = `mem`[_port_WIRE], clock
            |CHECK: connect out, port[jdx]
            |""".stripMargin
       )
diff --git a/src/test/scala-2/chiselTests/experimental/DataView.scala b/src/test/scala-2/chiselTests/experimental/DataView.scala
index 271a2a4a900..f4775e05240 100644
--- a/src/test/scala-2/chiselTests/experimental/DataView.scala
+++ b/src/test/scala-2/chiselTests/experimental/DataView.scala
@@ -184,12 +184,12 @@ class DataViewSpec extends AnyFlatSpec with Matchers {
     val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
     chirrtl should include("connect deq.valid, enq.valid")
     chirrtl should include("connect enq.ready, deq.ready")
-    chirrtl should include("connect deq.fizz, enq.bits.fizz")
-    chirrtl should include("connect deq.buzz, enq.bits.buzz")
+    chirrtl should include("connect deq.fizz, enq.`bits`.fizz")
+    chirrtl should include("connect deq.buzz, enq.`bits`.buzz")
     chirrtl should include("connect deq2.valid, enq.valid")
     chirrtl should include("connect enq.ready, deq2.ready")
-    chirrtl should include("connect deq2.fizz, enq.bits.fizz")
-    chirrtl should include("connect deq2.buzz, enq.bits.buzz")
+    chirrtl should include("connect deq2.fizz, enq.`bits`.fizz")
+    chirrtl should include("connect deq2.buzz, enq.`bits`.buzz")
   }
 
   it should "support viewing a Bundle as a Parent Bundle type" in {
@@ -274,7 +274,7 @@ class DataViewSpec extends AnyFlatSpec with Matchers {
       ifcMon.viewAsSupertype(chiselTypeOf(ifc)) :>= ifc
     }
     val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
-    chirrtl should include("invalidate ifc.foo.bits")
+    chirrtl should include("invalidate ifc.foo.`bits`")
     chirrtl should include("connect ifc.foo.ready, ifcMon.foo.ready")
   }
 
@@ -493,9 +493,9 @@ class DataViewSpec extends AnyFlatSpec with Matchers {
     val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
     val expected = List(
       "node x = and(a, b.value)",
-      "connect and, x",
+      "connect `and`, x",
       "node y = mux(cond, a, b.value)",
-      "connect mux, y",
+      "connect `mux`, y",
       "node aBits = bits(a, 3, 0)",
       "node bBits = bits(b.value, 3, 0)",
       "node abCat = cat(aBits, bBits)",
@@ -515,8 +515,8 @@ class DataViewSpec extends AnyFlatSpec with Matchers {
       fooOut := cat
     }
     val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
-    chirrtl should include("node cat = cat(barIn.foo, barIn.bar)")
-    chirrtl should include("connect fooOut, cat")
+    chirrtl should include("node `cat` = cat(barIn.foo, barIn.bar)")
+    chirrtl should include("connect fooOut, `cat`")
   }
 
   it should "be composable" in {
@@ -994,7 +994,7 @@ class DataViewSpec extends AnyFlatSpec with Matchers {
     }
     val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
     for (i <- 0 until 5) {
-      chirrtl should include(s"connect out$i.bits, in$i")
+      chirrtl should include(s"connect out$i.`bits`, in$i")
       chirrtl should include(s"connect out$i.valid, UInt<1>(0h1)")
     }
   }
diff --git a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala
index c3faae1d4e9..04f29209497 100644
--- a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala
+++ b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala
@@ -190,7 +190,7 @@ class InlineTestSpec extends AnyFlatSpec with Matchers with FileCheck with Chise
       | CHECK:        inst dut of ModuleWithTests
       | CHECK:        inst monitor of ProtocolMonitor
       | CHECK-NEXT:   connect monitor.clock, clock
-      | CHECK-NEXT:   connect monitor.reset, init
+      | CHECK-NEXT:   connect monitor.`reset`, init
       | CHECK-NEXT:   connect monitor.io.out, read(dut.monProbe).out
       | CHECK-NEXT:   connect monitor.io.in, read(dut.monProbe).in
       |
@@ -345,7 +345,7 @@ class InlineTestSpec extends AnyFlatSpec with Matchers with FileCheck with Chise
       s"""
       | CHECK:      module ModuleWithTests
       | CHECK-NEXT:   input clock : Clock
-      | CHECK-NEXT:   input reset : ${resetType}
+      | CHECK-NEXT:   input `reset` : ${resetType}
       |
       | CHECK:      public module test_ModuleWithTests_check1
       | CHECK-NEXT:   input clock : Clock
diff --git a/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala b/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
index d1279f2260e..be8681a83cf 100644
--- a/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
+++ b/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
@@ -255,7 +255,7 @@ class OpaqueTypeSpec extends AnyFlatSpec with Matchers {
     }
     // First check that it works when it should
     val chirrtl = ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(false)))
-    chirrtl should include("cat(in.valid, in.bits)")
+    chirrtl should include("cat(in.valid, in.`bits`)")
 
     val e1 = the[ChiselException] thrownBy {
       ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(true)), Array("--throw-on-first-error"))
diff --git a/src/test/scala-2/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala-2/chiselTests/experimental/hierarchy/InstanceSpec.scala
index abcad3391b7..aa9653d9495 100644
--- a/src/test/scala-2/chiselTests/experimental/hierarchy/InstanceSpec.scala
+++ b/src/test/scala-2/chiselTests/experimental/hierarchy/InstanceSpec.scala
@@ -532,8 +532,8 @@ class InstanceSpec extends AnyFunSpec with Matchers with Utils with FileCheck {
              |CHECK-NEXT: "tag":"bits"
              |
              |CHECK:      public module Top :
-             |CHECK:        connect i.in.valid, input.valid
-             |CHECK:        connect i.in.bits, input.bits
+             |CHECK:        connect i.in.valid, `input`.valid
+             |CHECK:        connect i.in.`bits`, `input`.`bits`
              |""".stripMargin
         )
     }
diff --git a/src/test/scala-2/chiselTests/experimental/hierarchy/InstantiateSpec.scala b/src/test/scala-2/chiselTests/experimental/hierarchy/InstantiateSpec.scala
index 268c7b22e85..237b17c9460 100644
--- a/src/test/scala-2/chiselTests/experimental/hierarchy/InstantiateSpec.scala
+++ b/src/test/scala-2/chiselTests/experimental/hierarchy/InstantiateSpec.scala
@@ -490,7 +490,7 @@ class InstantiateSpec extends AnyFunSpec with Matchers with FileCheck {
         val inst = Instantiate(new OneArg(3))
       })
       // Exact check simpler without FileCheck
-      chirrtl should include(s"inst inst of OneArg @[${info.asInstanceOf[SourceLine].serialize}]")
+      chirrtl should include(s"inst `inst` of OneArg @[${info.asInstanceOf[SourceLine].serialize}]")
     }
 
     it("should support BlackBoxes") {
diff --git a/src/test/scala-2/chiselTests/naming/PrefixSpec.scala b/src/test/scala-2/chiselTests/naming/PrefixSpec.scala
index a84afb9e280..cb378358ccb 100644
--- a/src/test/scala-2/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala-2/chiselTests/naming/PrefixSpec.scala
@@ -204,7 +204,7 @@ class PrefixSpec extends AnyPropSpec with Matchers with FileCheck {
         }
       }
     }
-    ChiselStage.emitCHIRRTL(new Test) should include("wire wire :")
+    ChiselStage.emitCHIRRTL(new Test) should include("wire `wire` :")
   }
 
   property("Prefixing should not leak into child modules, example 2") {
@@ -221,7 +221,7 @@ class PrefixSpec extends AnyPropSpec with Matchers with FileCheck {
         val child = Module(module)
       }
     }
-    ChiselStage.emitCHIRRTL(new Test) should include("wire wire")
+    ChiselStage.emitCHIRRTL(new Test) should include("wire `wire`")
   }
 
   property("Instance names should not be added to prefix") {
@@ -243,7 +243,7 @@ class PrefixSpec extends AnyPropSpec with Matchers with FileCheck {
       }
     }.fileCheck()(
       """|CHECK: input clock :
-         |CHECK: input reset :
+         |CHECK: input `reset` :
          |CHECK: input io :
          |""".stripMargin
     )
@@ -258,7 +258,7 @@ class PrefixSpec extends AnyPropSpec with Matchers with FileCheck {
         }
       }
     }
-    ChiselStage.emitCHIRRTL(new Test) should include("wire wire :")
+    ChiselStage.emitCHIRRTL(new Test) should include("wire `wire` :")
   }
 
   property("Prefixing should be caused by nested Iterable[Iterable[Data]]") {
diff --git a/src/test/scala-2/chiselTests/properties/PropertySpec.scala b/src/test/scala-2/chiselTests/properties/PropertySpec.scala
index 7138158d3c6..511c884a76e 100644
--- a/src/test/scala-2/chiselTests/properties/PropertySpec.scala
+++ b/src/test/scala-2/chiselTests/properties/PropertySpec.scala
@@ -521,11 +521,11 @@ class PropertySpec extends AnyFlatSpec with Matchers with FileCheck {
     }.fileCheck()(
       """|CHECK: output outgoing : { foo : String, flip bar : Integer}
          |CHECK: input incoming : { foo : String, flip bar : Integer}
-         |CHECK: wire wire : { foo : String, flip bar : Integer}
-         |CHECK: propassign incoming.bar, wire.bar
-         |CHECK: propassign wire.foo, incoming.foo
-         |CHECK: propassign wire.bar, outgoing.bar
-         |CHECK: propassign outgoing.foo, wire.foo
+         |CHECK: wire `wire` : { foo : String, flip bar : Integer}
+         |CHECK: propassign incoming.bar, `wire`.bar
+         |CHECK: propassign `wire`.foo, incoming.foo
+         |CHECK: propassign `wire`.bar, outgoing.bar
+         |CHECK: propassign outgoing.foo, `wire`.foo
          |""".stripMargin
     )
   }
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index e1f0ac4e5b8..6d0aa8c7ad2 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -58,10 +58,10 @@ class BulkConnectSpec extends AnyPropSpec with Matchers {
       deq <> enq
     })
 
-    chirrtl shouldNot include("connect wire, enq")
-    chirrtl should include("connect wire.bits, enq.bits")
-    chirrtl should include("connect wire.valid, enq.valid")
-    chirrtl should include("connect wire.ready, enq.ready")
+    chirrtl shouldNot include("connect `wire`, enq")
+    chirrtl should include("connect `wire`.`bits`, enq.`bits`")
+    chirrtl should include("connect `wire`.valid, enq.valid")
+    chirrtl should include("connect `wire`.ready, enq.ready")
     chirrtl should include("connect deq, enq")
   }
 
diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala
index f0305a4d7fc..73a6c210e51 100644
--- a/src/test/scala/chiselTests/BundleLiteralSpec.scala
+++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala
@@ -410,7 +410,7 @@ class BundleLiteralSpec extends AnyFlatSpec with Matchers with ChiselSim with Lo
       lit.b.getWidth should be(4)
       val cat = Cat(lit.a, lit.b)
     })
-    chirrtl should include("node cat = cat(UInt<4>(0h3), UInt<4>(0h3))")
+    chirrtl should include("node `cat` = cat(UInt<4>(0h3), UInt<4>(0h3))")
   }
 
   "Calling .asUInt on a Bundle literal" should "return a UInt literal and work outside of elaboration" in {
diff --git a/src/test/scala/chiselTests/DecoupledSpec.scala b/src/test/scala/chiselTests/DecoupledSpec.scala
index 58feef079c5..f6b922f9be6 100644
--- a/src/test/scala/chiselTests/DecoupledSpec.scala
+++ b/src/test/scala/chiselTests/DecoupledSpec.scala
@@ -28,9 +28,9 @@ class DecoupledSpec extends AnyFlatSpec with Matchers with FileCheck {
         val deq = IO(Decoupled(UInt(8.W)))
         deq <> enq.map(_ + 1.U)
       })
-      .fileCheck()("""|CHECK: node [[node1:[a-zA-Z0-9_]+]] = add(enq.bits, UInt<1>(0h1))
+      .fileCheck()("""|CHECK: node [[node1:[a-zA-Z0-9_]+]] = add(enq.`bits`, UInt<1>(0h1))
                       |CHECK: node [[node2:[a-zA-Z0-9_]+]] = tail([[node1]], 1)
-                      |CHECK: connect [[result:[a-zA-Z0-9_]+]].bits, [[node2]]
+                      |CHECK: connect [[result:[a-zA-Z0-9_]+]].`bits`, [[node2]]
                       |# Check for back-pressure (ready signal is driven in the opposite direction of bits + valid)
                       |CHECK: connect enq.ready, [[result]].ready
                       |CHECK: connect deq, [[result]]
@@ -67,18 +67,18 @@ class DecoupledSpec extends AnyFlatSpec with Matchers with FileCheck {
     // Check for data assignment
     chirrtl should include("""wire _deq_map_bits : { foo : UInt<8>, bar : UInt<8>, fizz : UInt<1>, buzz : UInt<1>}""")
 
-    chirrtl should include("""node _deq_map_bits_res_foo_T = add(enq.bits.foo, UInt<1>(0h1)""")
+    chirrtl should include("""node _deq_map_bits_res_foo_T = add(enq.`bits`.foo, UInt<1>(0h1)""")
     chirrtl should include("""node _deq_map_bits_res_foo_T_1 = tail(_deq_map_bits_res_foo_T, 1)""")
     chirrtl should include("""connect _deq_map_bits.foo, _deq_map_bits_res_foo_T_1""")
 
-    chirrtl should include("""node _deq_map_bits_res_bar_T = sub(enq.bits.bar, UInt<1>(0h1)""")
+    chirrtl should include("""node _deq_map_bits_res_bar_T = sub(enq.`bits`.bar, UInt<1>(0h1)""")
     chirrtl should include("""node _deq_map_bits_res_bar_T_1 = tail(_deq_map_bits_res_bar_T, 1)""")
     chirrtl should include("""connect _deq_map_bits.bar, _deq_map_bits_res_bar_T_1""")
 
     chirrtl should include("""connect _deq_map_bits.fizz, UInt<1>(0h0)""")
     chirrtl should include("""connect _deq_map_bits.buzz, UInt<1>(0h1)""")
 
-    chirrtl should include("""connect _deq_map.bits, _deq_map_bits""")
+    chirrtl should include("""connect _deq_map.`bits`, _deq_map_bits""")
     chirrtl should include("""connect deq, _deq_map""")
 
     // Check for back-pressure (ready signal is driven in the opposite direction of bits + valid)
@@ -102,8 +102,8 @@ class DecoupledSpec extends AnyFlatSpec with Matchers with FileCheck {
     chirrtl should include("""wire _deq_map : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}""")
 
     // Check for data assignment
-    chirrtl should include("""node _deq_map_bits = and(enq.bits.foo, enq.bits.bar)""")
-    chirrtl should include("""connect _deq_map.bits, _deq_map_bits""")
+    chirrtl should include("""node _deq_map_bits = and(enq.`bits`.foo, enq.`bits`.bar)""")
+    chirrtl should include("""connect _deq_map.`bits`, _deq_map_bits""")
     chirrtl should include("""connect deq, _deq_map""")
 
     // Check for back-pressure (ready signal is driven in the opposite direction of bits + valid)
diff --git a/src/test/scala/chiselTests/FirrtlKeywordEscapingSpec.scala b/src/test/scala/chiselTests/FirrtlKeywordEscapingSpec.scala
new file mode 100644
index 00000000000..399f1c56e4d
--- /dev/null
+++ b/src/test/scala/chiselTests/FirrtlKeywordEscapingSpec.scala
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+
+import chisel3._
+import chisel3.testing.scalatest.FileCheck
+import circt.stage.ChiselStage
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+class FirrtlKeywordEscapingSpec extends AnyFlatSpec with Matchers with FileCheck {
+
+  behavior.of("FIRRTL keyword escaping")
+
+  it should "escape FIRRTL type keywords used as port names" in {
+    ChiselStage.emitCHIRRTL {
+      new RawModule {
+        val UInt = IO(chisel3.UInt(2.W))
+        UInt :<= 3.U
+      }
+    }.fileCheck() {
+      """|CHECK: output `UInt` : UInt<2>
+         |CHECK: connect `UInt`, UInt<2>(0h3)
+         |""".stripMargin
+    }
+  }
+
+  it should "compile the user's example to SystemVerilog without errors" in {
+    class Foo extends RawModule {
+      val UInt = IO(chisel3.UInt(2.W))
+      UInt :<= 3.U
+    }
+
+    ChiselStage
+      .emitCHIRRTL(new Foo)
+      .fileCheck() {
+        """|CHECK: output `UInt` : UInt<2>
+           |CHECK: connect `UInt`, UInt<2>(0h3)
+           |""".stripMargin
+      }
+
+    // This should not throw an error
+    val sv = ChiselStage.emitSystemVerilog(
+      gen = new Foo,
+      args = Array("--throw-on-first-error")
+    )
+    sv should not be empty
+  }
+
+  it should "escape FIRRTL keywords used as wire names" in {
+    ChiselStage
+      .emitCHIRRTL(new Module {
+        val io = IO(new Bundle {})
+        val wire = Wire(chisel3.UInt(8.W))
+        val reg = Wire(chisel3.UInt(8.W))
+        val node = Wire(chisel3.UInt(8.W))
+        val Clock = Wire(chisel3.UInt(8.W))
+        val Reset = Wire(chisel3.UInt(8.W))
+        val mux = Wire(chisel3.UInt(8.W))
+
+        wire := 1.U
+        reg := 2.U
+        node := 3.U
+        Clock := 4.U
+        Reset := 5.U
+        mux := 6.U
+      })
+      .fileCheck() {
+        """|CHECK: wire `wire` : UInt<8>
+           |CHECK: wire `reg` : UInt<8>
+           |CHECK: wire `node` : UInt<8>
+           |CHECK: wire `Clock` : UInt<8>
+           |CHECK: wire `Reset` : UInt<8>
+           |CHECK: wire `mux` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape FIRRTL statement keywords" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val when = IO(Output(chisel3.UInt(8.W)))
+        val skip = IO(Output(chisel3.UInt(8.W)))
+        val inst = IO(Output(chisel3.UInt(8.W)))
+
+        when :<= 1.U
+        skip :<= 2.U
+        inst :<= 3.U
+      })
+      .fileCheck() {
+        """|CHECK: output `when` : UInt<8>
+           |CHECK: output `skip` : UInt<8>
+           |CHECK: output `inst` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape FIRRTL primop keywords" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val add = IO(Output(chisel3.UInt(8.W)))
+        val sub = IO(Output(chisel3.UInt(8.W)))
+        val mul = IO(Output(chisel3.UInt(8.W)))
+        val and = IO(Output(chisel3.UInt(8.W)))
+        val or = IO(Output(chisel3.UInt(8.W)))
+        val xor = IO(Output(chisel3.UInt(8.W)))
+
+        add :<= 1.U
+        sub :<= 2.U
+        mul :<= 3.U
+        and :<= 4.U
+        or :<= 5.U
+        xor :<= 6.U
+      })
+      .fileCheck() {
+        """|CHECK: output `add` : UInt<8>
+           |CHECK: output `sub` : UInt<8>
+           |CHECK: output `mul` : UInt<8>
+           |CHECK: output `and` : UInt<8>
+           |CHECK: output `or` : UInt<8>
+           |CHECK: output `xor` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape module-level keywords" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val module = IO(Output(chisel3.UInt(8.W)))
+        val circuit = IO(Output(chisel3.UInt(8.W)))
+        val input = IO(Output(chisel3.UInt(8.W)))
+        val output = IO(Output(chisel3.UInt(8.W)))
+
+        module :<= 1.U
+        circuit :<= 2.U
+        input :<= 3.U
+        output :<= 4.U
+      })
+      .fileCheck() {
+        """|CHECK: output `module` : UInt<8>
+           |CHECK: output `circuit` : UInt<8>
+           |CHECK: output `input` : UInt<8>
+           |CHECK: output `output` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape connect-like keywords" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val connect = IO(Output(chisel3.UInt(8.W)))
+        val invalidate = IO(Output(chisel3.UInt(8.W)))
+        val attach = IO(Output(chisel3.UInt(8.W)))
+
+        connect :<= 1.U
+        invalidate :<= 2.U
+        attach :<= 3.U
+      })
+      .fileCheck() {
+        """|CHECK: output `connect` : UInt<8>
+           |CHECK: output `invalidate` : UInt<8>
+           |CHECK: output `attach` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape command keywords" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val printf = IO(Output(chisel3.UInt(8.W)))
+        val assert = IO(Output(chisel3.UInt(8.W)))
+        val assume = IO(Output(chisel3.UInt(8.W)))
+        val cover = IO(Output(chisel3.UInt(8.W)))
+
+        printf :<= 1.U
+        assert :<= 2.U
+        assume :<= 3.U
+        cover :<= 4.U
+      })
+      .fileCheck() {
+        """|CHECK: output `printf` : UInt<8>
+           |CHECK: output `assert` : UInt<8>
+           |CHECK: output `assume` : UInt<8>
+           |CHECK: output `cover` : UInt<8>
+           |""".stripMargin
+      }
+  }
+
+  it should "escape CIRCT-specific keywords like Unknown" in {
+    ChiselStage
+      .emitCHIRRTL(new RawModule {
+        val Unknown = IO(Output(chisel3.UInt(8.W)))
+        val Bool = IO(Output(chisel3.UInt(1.W)))
+        val reset = IO(Output(chisel3.UInt(1.W)))
+
+        Unknown :<= 42.U
+        Bool :<= 1.U
+        reset :<= 0.U
+      })
+      .fileCheck() {
+        """|CHECK: output `Unknown` : UInt<8>
+           |CHECK: output `Bool` : UInt<1>
+           |CHECK: output `reset` : UInt<1>
+           |""".stripMargin
+      }
+  }
+}
diff --git a/src/test/scala/chiselTests/LTLSpec.scala b/src/test/scala/chiselTests/LTLSpec.scala
index 69dcc55797b..933e8077484 100644
--- a/src/test/scala/chiselTests/LTLSpec.scala
+++ b/src/test/scala/chiselTests/LTLSpec.scala
@@ -310,7 +310,7 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselSim {
         prop(a)
       })
       val sourceLoc = "@[Foo.scala 1:2]"
-      chirrtl should include("node has_been_reset = intrinsic(circt_has_been_reset : UInt<1>, clock, reset)")
+      chirrtl should include("node has_been_reset = intrinsic(circt_has_been_reset : UInt<1>, clock, `reset`)")
       chirrtl should include("node disable = eq(has_been_reset, UInt<1>(0h0))")
       chirrtl should include(f"node ltl_clock = intrinsic(circt_ltl_clock : UInt<1>, a, clock) $sourceLoc")
       chirrtl should include(f"node _T = eq(disable, UInt<1>(0h0)) $sourceLoc")
diff --git a/src/test/scala/chiselTests/PortSpec.scala b/src/test/scala/chiselTests/PortSpec.scala
index aea63998e2b..dc4f6fac051 100644
--- a/src/test/scala/chiselTests/PortSpec.scala
+++ b/src/test/scala/chiselTests/PortSpec.scala
@@ -29,7 +29,7 @@ class PortSpec extends AnyFlatSpec with Matchers with FileCheck {
       .fileCheck()(
         """|CHECK:      public module Dummy :
            |CHECK-NEXT:   input clock : Clock @[src/test/scala/chiselTests/PortSpec.scala 16:
-           |CHECK-NEXT:   input reset : UInt<1> @[src/test/scala/chiselTests/PortSpec.scala 16:
+           |CHECK-NEXT:   input `reset` : UInt<1> @[src/test/scala/chiselTests/PortSpec.scala 16:
            |CHECK-NEXT:   output in : { flip foo : UInt<1>, flip bar : UInt<8>} @[src/test/scala/chiselTests/PortSpec.scala 17:
            |CHECK-NEXT:   output out : UInt<1> @[src/test/scala/chiselTests/PortSpec.scala 18:
            |""".stripMargin
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index 21a8f114a2c..f39bf448963 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -104,14 +104,14 @@ class ResetSpec extends AnyFlatSpec with Matchers {
     val fir = ChiselStage.emitCHIRRTL(new Module with RequireSyncReset {
       reset shouldBe a[Bool]
     })
-    fir should include("input reset : UInt<1>")
+    fir should include("input `reset` : UInt<1>")
   }
 
   they should "be able to force implicit reset to be asynchronous" in {
     val fir = ChiselStage.emitCHIRRTL(new Module with RequireAsyncReset {
       reset shouldBe an[AsyncReset]
     })
-    fir should include("input reset : AsyncReset")
+    fir should include("input `reset` : AsyncReset")
   }
 
   they should "be able to override the value of the implicit reset" in {
@@ -149,12 +149,12 @@ class ResetSpec extends AnyFlatSpec with Matchers {
     val firAsync = ChiselStage.emitCHIRRTL(new MyModule(true) {
       reset shouldBe an[AsyncReset]
     })
-    firAsync should include("input reset : AsyncReset")
+    firAsync should include("input `reset` : AsyncReset")
 
     val firSync = ChiselStage.emitCHIRRTL(new MyModule(false) {
       reset shouldBe a[Bool]
     })
-    firSync should include("input reset : UInt<1>")
+    firSync should include("input `reset` : UInt<1>")
   }
 
   "Chisel" should "error if sync and async modules are nested" in {
diff --git a/src/test/scala/chiselTests/SourceLocatorSpec.scala b/src/test/scala/chiselTests/SourceLocatorSpec.scala
index 138b7b1c8e0..be560cde197 100644
--- a/src/test/scala/chiselTests/SourceLocatorSpec.scala
+++ b/src/test/scala/chiselTests/SourceLocatorSpec.scala
@@ -142,14 +142,14 @@ class SourceLocatorSpec extends AnyFunSpec with Matchers {
   describe("(4) SourceLocator simple definitions") {
     it("(4.a): Simple definitions should have a source locator") {
       val chirrtl = emitCHIRRTL(new SimpleDefinitions)
-      chirrtl should include(s"wire wire : UInt<8> @[$thisFile 46:${col(20, 30)}]")
-      chirrtl should include(s"reg reg : UInt<8>, clock @[$thisFile 47:${col(18, 28)}]")
-      chirrtl should include(s"regreset regInit : UInt<8>, clock, reset, UInt<8>(0h0) @[$thisFile 48:${col(26, 35)}]")
+      chirrtl should include(s"wire `wire` : UInt<8> @[$thisFile 46:${col(20, 30)}]")
+      chirrtl should include(s"reg `reg` : UInt<8>, clock @[$thisFile 47:${col(18, 28)}]")
+      chirrtl should include(s"regreset regInit : UInt<8>, clock, `reset`, UInt<8>(0h0) @[$thisFile 48:${col(26, 35)}]")
       chirrtl should include(s"reg regNext : UInt, clock @[$thisFile 49:${col(26, 35)}]")
       chirrtl should include(s"reg regEnable : UInt<8>, clock @[$thisFile 50:${col(30, 47)}]")
       chirrtl should include(s"input port : UInt<1> @[$thisFile 51:${col(18, 32)}]")
-      chirrtl should include(s"inst inst of RawModuleChild @[$thisFile 52:${col(22, 41)}]")
-      chirrtl should include(s"cmem mem : UInt<8>[1024] @[$thisFile 53:${col(18, 34)}]")
+      chirrtl should include(s"inst `inst` of RawModuleChild @[$thisFile 52:${col(22, 41)}]")
+      chirrtl should include(s"cmem `mem` : UInt<8>[1024] @[$thisFile 53:${col(18, 34)}]")
     }
   }
 }
diff --git a/src/test/scala/chiselTests/ValidSpec.scala b/src/test/scala/chiselTests/ValidSpec.scala
index 46b0d7dec6d..90a254558c9 100644
--- a/src/test/scala/chiselTests/ValidSpec.scala
+++ b/src/test/scala/chiselTests/ValidSpec.scala
@@ -17,10 +17,10 @@ class ValidSpec extends AnyFlatSpec with Matchers {
     })
 
     // Check for data assignment
-    chirrtl should include("""node _out_map_bits_T = add(in.bits, UInt<1>(0h1))""")
+    chirrtl should include("""node _out_map_bits_T = add(in.`bits`, UInt<1>(0h1))""")
     chirrtl should include("""node _out_map_bits = tail(_out_map_bits_T, 1)""")
-    chirrtl should include("""connect _out_map.bits, _out_map_bits""")
-    chirrtl should include("""connect out.bits, _out_map.bits""")
+    chirrtl should include("""connect _out_map.`bits`, _out_map_bits""")
+    chirrtl should include("""connect out.`bits`, _out_map.`bits`""")
 
     // Check for valid assignment
     chirrtl should include("""connect _out_map.valid, in.valid""")
@@ -57,20 +57,20 @@ class ValidSpec extends AnyFlatSpec with Matchers {
     // Check for data assignment
     chirrtl should include("""wire _out_map_bits : { foo : UInt<8>, bar : UInt<8>, fizz : UInt<1>, buzz : UInt<1>}""")
 
-    chirrtl should include("""node _out_map_bits_res_foo_T = add(in.bits.foo, UInt<1>(0h1)""")
+    chirrtl should include("""node _out_map_bits_res_foo_T = add(in.`bits`.foo, UInt<1>(0h1)""")
     chirrtl should include("""node _out_map_bits_res_foo_T_1 = tail(_out_map_bits_res_foo_T, 1)""")
     chirrtl should include("""connect _out_map_bits.foo, _out_map_bits_res_foo_T_1""")
 
-    chirrtl should include("""node _out_map_bits_res_bar_T = sub(in.bits.bar, UInt<1>(0h1)""")
+    chirrtl should include("""node _out_map_bits_res_bar_T = sub(in.`bits`.bar, UInt<1>(0h1)""")
     chirrtl should include("""node _out_map_bits_res_bar_T_1 = tail(_out_map_bits_res_bar_T, 1)""")
     chirrtl should include("""connect _out_map_bits.bar, _out_map_bits_res_bar_T_1""")
 
     chirrtl should include("""connect _out_map_bits.fizz, UInt<1>(0h0)""")
     chirrtl should include("""connect _out_map_bits.buzz, UInt<1>(0h1)""")
 
-    chirrtl should include("""connect _out_map.bits, _out_map_bits""")
+    chirrtl should include("""connect _out_map.`bits`, _out_map_bits""")
     for ((field, _) <- (new TestBundle).elements) {
-      chirrtl should include(s"""connect out.bits.$field, _out_map.bits.$field""")
+      chirrtl should include(s"""connect out.`bits`.$field, _out_map.`bits`.$field""")
     }
 
     // Check for valid assignment
@@ -95,9 +95,9 @@ class ValidSpec extends AnyFlatSpec with Matchers {
     chirrtl should include("""wire _out_map : { valid : UInt<1>, bits : UInt<8>}""")
 
     // Check for data assignment
-    chirrtl should include("""node _out_map_bits = and(in.bits.foo, in.bits.bar)""")
-    chirrtl should include("""connect _out_map.bits, _out_map_bits""")
-    chirrtl should include("""connect out.bits, _out_map.bits""")
+    chirrtl should include("""node _out_map_bits = and(in.`bits`.foo, in.`bits`.bar)""")
+    chirrtl should include("""connect _out_map.`bits`, _out_map_bits""")
+    chirrtl should include("""connect out.`bits`, _out_map.`bits`""")
 
     // Check for valid assignment
     chirrtl should include("""connect _out_map.valid, in.valid""")
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index 6024e98946a..9b6b33cbc77 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -86,7 +86,7 @@ class VecLiteralSpec extends AnyFreeSpec with Matchers with ChiselSim {
     firrtl should include("""connect _y_WIRE[1], UInt<8>(0hcd)""")
     firrtl should include("""connect _y_WIRE[2], UInt<8>(0hef)""")
     firrtl should include("""connect _y_WIRE[3], UInt<8>(0hff)""")
-    firrtl should include("""regreset y : UInt<8>[4], clock, reset, _y_WIRE""".stripMargin)
+    firrtl should include("""regreset y : UInt<8>[4], clock, `reset`, _y_WIRE""".stripMargin)
   }
 
   // NOTE: I had problems where this would not work if this class declaration was inside test scope
@@ -101,7 +101,7 @@ class VecLiteralSpec extends AnyFreeSpec with Matchers with ChiselSim {
     firrtl should include("""invalidate _y_WIRE[1]""")
     firrtl should include("""connect _y_WIRE[2], UInt<8>(0hef)""")
     firrtl should include("""connect _y_WIRE[3], UInt<8>(0hff)""")
-    firrtl should include("""regreset y : UInt<8>[4], clock, reset, _y_WIRE""".stripMargin)
+    firrtl should include("""regreset y : UInt<8>[4], clock, `reset`, _y_WIRE""".stripMargin)
   }
 
   class ResetRegWithPartialVecLiteral extends Module {
diff --git a/src/test/scala/chiselTests/VerificationSpec.scala b/src/test/scala/chiselTests/VerificationSpec.scala
index df365c72fc3..1d32f8f1f06 100644
--- a/src/test/scala/chiselTests/VerificationSpec.scala
+++ b/src/test/scala/chiselTests/VerificationSpec.scala
@@ -30,7 +30,7 @@ class VerificationSpec extends AnyPropSpec with FileCheck {
          |CHECK:      node _T_3 = neq(io.in, UInt<2>(0h2))
          |CHECK:      assume(clock, _T_3, UInt<1>(0h1), "Assumption failed at
          |CHECK:      node _T_5 = eq(io.out, io.in)
-         |CHECK:      node _T_6 = eq(reset, UInt<1>(0h0))
+         |CHECK:      node _T_6 = eq(`reset`, UInt<1>(0h0))
          |CHECK:      intrinsic(circt_chisel_ifelsefatal<format = "Assertion failed: io.in:%d is equal to io.out:%d\n", label = "chisel3_builtin">, clock, _T_5, _T_6, io.in, io.out)
          |""".stripMargin
     }
diff --git a/src/test/scala/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala
index 7001f59c84e..f0d00a558be 100644
--- a/src/test/scala/chiselTests/WireSpec.scala
+++ b/src/test/scala/chiselTests/WireSpec.scala
@@ -32,7 +32,7 @@ class WireSpec extends AnyFlatSpec with Matchers {
     }
 
     val chirrtl = ChiselStage.emitCHIRRTL(new Dummy)
-    chirrtl should include("wire wire : UInt<1>")
+    chirrtl should include("wire `wire` : UInt<1>")
     chirrtl should include("wire wire2 : UInt<1>")
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
index 264a895b058..670fbfa6ee8 100644
--- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
+++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -43,7 +43,7 @@ class FlatIOSpec extends AnyFlatSpec with Matchers with FileCheck {
     ChiselStage
       .emitCHIRRTL(new MyModule)
       .fileCheck()(
-        """|CHECK:      connect out.bits, bits
+        """|CHECK:      connect out.`bits`, `bits`
            |CHECK-NEXT: connect out.valid, valid
            |"""".stripMargin
       )
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 1964297b689..360209b860a 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -455,7 +455,7 @@ class NamePluginSpec extends AnyFlatSpec with Matchers with FileCheck {
       )
       .fileCheck("--implicit-check-not=wire")(
         """|CHECK: input clock :
-           |CHECK: input reset :
+           |CHECK: input `reset` :
            |CHECK: output foo_1 :
            |CHECK: input foo_in :
            |CHECK: reg foo_out_REG :