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Z180 Opcode table

Some - partially implemented, not fully written
Test - completely implemented, not fully tested
Fail - incorrectly implemented, failing tests
ok  - completely implemented and fully tested

All other opcodes are treated as invalid instructions.

opcode opcode 1 opcode 2 opcode 3 operation SZHPNC Status
00_000_000 NOP ······ ok
00_ww0_001 n m LD ww, mn ······ ok
00_000_010 LD (BC), A ······ ok
00_ww0_011 INC ww ······ ok
00_ggg_100 INC g ↑↑↑VR· ok
00_ggg_101 DEC g ↑↑↑VS· ok
00_ggg_110 m LD g, m ······ ok
00_110_110 m LD (HL), m ······ ok
00_000_111 RLC A ··R·R↑ ok
00_001_000 EX AF, AF' ······ Test
00_ww1_001 ADD HL, ww ··X·R↑ ok
00_001_010 LD A, (BC) ······ ok
00_ww1_011 DEC ww ······ ok
00_001_111 RRCA ··R·R↑ ok
00_010_000 j-2 DJNZ j ······ Test
00_010_010 LD (DE), A ······ ok
00_010_111 RL A ··R·R↑ ok
00_011_000 j-2 JR j ······ Test
00_011_010 LD A, (DE) ······ ok
00_011_111 RRA ··R·R↑ ok
00_100_000 j-2 JR NZ, j ······ Test
00_100_010 n m LD (mn), HL ······ ok
00_100_111 DAA ↑↑↑P·↑ Fail
00_101_000 j-2 JR Z, j ······ Test
00_101_010 n m LD HL, (mn) ······ ok
00_101_111 CPL ··S·S· ok
00_110_000 j-2 JR NC, j ······ Test
00_110_010 n m LD (mn), A ······ ok
00_110_100 INC (HL) ↑↑↑VR· ok
00_110_101 DEC (HL) ↑↑↑VS· ok
00_110_110 m LD (HL), m ······ ok
00_110_111 SCF ··R·RS ok
00_111_000 j-2 JR C, j ······ Test
00_111_010 n m LD A, (mn) ······ ok
00_111_111 CCF ··R·R↑ ok
01_ggg_ggg LD g, g' ······ ok
01_ggg_110 LD g, (HL) ······ ok
01_110_ggg LD (HL), g ······ ok
01_110_110 HALT ······ Test
10_000_ggg ADD A, g ↑↑↑VR↑ ok
10_000_110 ADD A, (HL) ↑↑↑VR↑ ok
10_001_ggg ADC A, g ↑↑↑VR↑ ok
10_001_110 ADC A, (HL) ↑↑↑VR↑ ok
10_010_ggg SUB g ↑↑↑VS↑ ok
10_010_110 SUB (HL) ↑↑↑VS↑ ok
10_011_ggg SBC A, g ↑↑↑VS↑ ok
10_011_110 SBC A, (HL) ↑↑↑VS↑ ok
10_100_ggg AND g ↑↑SPRR ok
10_100_110 AND (HL) ↑↑SPRR ok
10_101_ggg XOR g ↑↑SPRR ok
10_101_110 XOR (HL) ↑↑SPRR ok
10_110_ggg OR g ↑↑RPRR ok
10_110_110 OR (HL) ↑↑RPRR ok
10_111_ggg CP g ↑↑↑VS↑ ok
10_111_110 CP (HL) ↑↑↑VS↑ ok
11_fff_000 RET f ······ Test
11_zz0_001 POP zz ······ ok
11_fff_010 n m JP f, mn ······ Test
11_000_011 n m JP mn ······ Test
11_zz0_101 PUSH zz ······ ok
11_000_110 m ADD A, m ↑↑↑VR↑ ok
11_vvv_111 RST v ······ Test
11_001_001 RET ······ Test
11_001_011 00_000_ggg RLC g ↑↑RPR↑ ok
00_000_110 RLC (HL) ↑↑RPR↑ ok
00_001_ggg RRC g ↑↑RPR↑ ok
00_001_110 RRC (HL) ↑↑RPR↑ ok
00_010_ggg RL g ↑↑RPR↑ ok
00_010_110 RL (HL) ↑↑RPR↑ ok
00_011_ggg RR g ↑↑RPR↑ ok
00_011_110 RR (HL) ↑↑RPR↑ ok
00_100_ggg SLA g ↑↑RPR↑ ok
00_100_110 SLA (HL) ↑↑RPR↑ ok
00_101_ggg SRA g ↑↑RPR↑ ok
00_101_110 SRA (HL) ↑↑RPR↑ ok
00_111_ggg SRL g ↑↑RPR↑ ok
00_111_110 SRL (HL) ↑↑RPR↑ ok
01_bbb_ggg BIT b, g X↑SXR· ok
01_bbb_110 BIT b, (HL) X↑SXR· ok
10_bbb_ggg RES b, g ······ ok
10_bbb_110 RES b, (HL) ······ ok
11_bbb_ggg SET b, g ······ ok
11_bbb_110 SET b, (HL) ······ ok
11_fff_100 n m CALL f, mn ······ Test
11_001_101 n m CALL mn ······ Test
11_001_110 m ADC A, m ↑↑↑VR↑ ok
11_010_011 m OUT (m), A ······ Test
11_010_110 m SUB m ↑↑↑VS↑ ok
11_011_001 EXX ······ Test
11_011_011 m IN A, (m) ······ Test
11_011_101 00_110_101 d DEC (IX + d) ↑↑↑VS· ok
00_110_100 d INC (IX + d) ↑↑↑VS· ok
00_110_110 d m LD (IX + d), m ······ ok
00_xx1_001 ADD IX, xx ··X·R↑ ok
00_100_001 n m LD IX, mn ······ ok
00_100_010 n m LD (mn), IX ······ ok
00_100_011 INC IX ······ ok
00_101_010 n m LD IX, (mn) ······ ok
00_101_011 DEC IX ······ ok
01_ggg_110 d LD g, (IX + d) ······ ok
01_110_ggg d LD (IX + d), g ······ ok
10_000_110 d ADD A, (IX + d) ↑↑↑VR↑ ok
10_001_110 d ADC A, (IX + d) ↑↑↑VR↑ ok
10_010_110 d SUB (IX + d) ↑↑↑VS↑ ok
10_011_110 d SBC (IX + d) ↑↑↑VS↑ ok
10_100_110 d AND (IX + d) ↑↑SPRR ok
10_101_110 d XOR (IX + d) ↑↑RPRR ok
10_110_110 d OR (IX + d) ↑↑RPRR ok
10_111_110 d CP (IX + d) ↑↑↑VR↑ ok
11_001_011 d 00_000_110 RLC (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_001_110 RRC (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_010_110 RL (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_011_110 RR (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_100_110 SLA (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_101_110 SRA (IX + d) ↑↑RPR↑ ok
11_001_011 d 00_111_110 SRL (IX + d) ↑↑RPR↑ ok
11_001_011 d 01_bbb_110 BIT b, (IX + d) X↑SXR· ok
11_001_011 d 10_bbb_110 RES b, (IX + d) ······ ok
11_001_011 d 11_bbb_110 SET b, (IX + d) ······ ok
11_100_001 POP IX ······ ok
11_100_011 EX (SP), IX ······ Test
11_100_101 PUSH IX ······ ok
11_101_001 JP (IX) ······ Test
11_111_001 LD SP, IX ······ ok
11_011_110 m SBC A, m ↑↑↑VS↑ ok
11_100_011 EX (SP), HL ······ Test
11_100_110 m AND m ↑↑SPRR ok
11_101_001 JP (HL) ······ Test
11_101_011 EX DE, HL ······ Test
11_101_101 00_ggg_000 m IN0 g, (m) ** ↑↑RPR·
00_110_000 m IN0 (m) ** ↑↑RPR·
00_ggg_001 m OUT0 (m), g ** ······ Some
00_ggg_100 TST g ** ↑↑SPRR
00_110_100 TST (HL) ** ↑↑SPRR
01_ww0_010 SBC HL, ww ↑↑XVS↑ ok
01_ww0_011 n m LD (mn), ww ······ ok
01_ww1_010 ADC HL, ww ↑↑XVR↑ ok
01_ww1_011 n m LD ww, (mn) ······ ok
01_ww1_100 MLT ww ** ······
01_ggg_000 IN g, (C) ↑↑RPR·
01_ggg_001 OUT (C), g ······
01_000_100 NEG ↑↑↑YS↑ ok
01_000_101 RETN ······
01_000_110 IM0 ······
01_000_111 LD I, A ······ Test
01_001_101 RETI ······
01_001_111 LD R, A ······ Test
01_010_110 IM1 ······
01_010_111 LD A, I ↑↑R2R·
01_011_110 IM2 ······
01_011_111 LD A, R ↑↑R2R·
01_100_100 m TST m** ↑↑SPRR
01_100_111 RRD ↑↑RPR· ok
01_101_111 RLD ↑↑RPR· ok
01_110_100 m TSTIO m ** ↑↑SPRR
01_110_110 SLP ** ······
10_000_011 OTIM ** ↑↑↑P↑↑
10_001_011 OTDM ** ↑↑↑P↑↑
10_010_011 OTIMR ** RSRS↑R
10_011_011 OTDMR ** RSRS↑R
10_100_000 LDI ··R↑R· ok
10_100_001 CPI ↑↑↑↑S·
10_100_010 INI X↑XX↑X
10_100_011 OUTI X↑XX↑X
10_101_000 LDD ··R↑R· ok
10_101_001 CPD ↑↑↑↑S· Fail
10_101_010 IND X↑XX↑X
10_101_011 OUTD X↑XX↑X
10_110_000 LDIR ··R↑R· ok
10_110_001 CPIR ↑↑↑↑S·
10_110_010 INIR XSXX↑X
10_110_011 OTIR XSXX↑X
10_111_000 LDDR ··RRR· ok
10_111_001 CPDR ↑↑↑↑S· Fail
10_111_010 INDR XSXX↑X
10_111_011 OTDR XSXX↑X
11_101_110 m XOR m ↑↑SPRR ok
11_110_011 DI ······ Test
11_110_110 m OR m ↑↑RPRR ok
11_111_001 LD SP, HL ······ ok
11_111_011 EI ······ Test
11_111_101 00_110_101 d DEC (IY + d) ↑↑↑VS· ok
00_110_100 d INC (IY + d) ↑↑↑VS· ok
00_110_110 d m LD (IY + d), m ······ ok
00_yy1_001 ADD IY, yy ··X·R↑ ok
00_100_001 n m LD IY, mn ······ ok
00_100_010 n m LD (mn), IY ······ ok
00_100_011 INC IY ······ ok
00_101_010 n m LD IX, (mn) ······ ok
00_101_011 DEC IY ······ ok
01_ggg_110 d LD g, (IY + d) ······ ok
01_110_ggg d LD (IY + d), g ······ ok
10_000_110 d ADD A, (IY + d) ↑↑↑VR↑ ok
10_001_110 d ADC A, (IY + d) ↑↑↑VR↑ ok
10_010_110 d SUB (IY + d) ↑↑↑VS↑ ok
10_011_110 d SBC (IY + d) ↑↑↑VS↑ ok
10_100_110 d AND (IY + d) ↑↑SPRR ok
10_101_110 d XOR (IY + d) ↑↑RPRR ok
10_110_110 d OR (IY + d) ↑↑RPRR ok
10_111_110 d CP (IY + d) ↑↑↑VR↑ ok
11_001_011 d 00_000_110 RLC (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_001_110 RRC (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_010_110 RL (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_011_110 RR (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_100_110 SLA (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_101_110 SRA (IY + d) ↑↑RPR↑ ok
11_001_011 d 00_111_110 SRL (IY + d) ↑↑RPR↑ ok
11_001_011 d 01_bbb_110 BIT b, (IY + d) X↑SXR· ok
11_001_011 d 10_bbb_110 RES b, (IY + d) ······ ok
11_001_011 d 11_bbb_110 SET b, (IY + d) ······ ok
11_100_001 POP IY ······ ok
11_100_011 EX (SP), IY ······ ok
11_100_101 PUSH IY ······ ok
11_101_001 JP (IY) ······ Test
11_111_001 LD SP, IY ······ ok
11_111_110 m CP m ↑↑↑VR↑ ok