refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio

Author: songruo

components/esp_driver_gpio/src/dedic_gpio.c

@@ -17,6 +17,7 @@
 #include "esp_cpu.h"
 #include "soc/soc_caps_full.h"
 #include "soc/io_mux_reg.h"
+#include "hal/dedic_gpio_caps.h"
 #include "hal/dedic_gpio_cpu_ll.h"
 #include "esp_private/gpio.h"
 #include "esp_private/periph_ctrl.h"
@@ -25,10 +26,10 @@
 #include "driver/dedic_gpio.h"
 #include "hal/dedic_gpio_periph.h"
 
-#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS)
 #include "soc/dedic_gpio_struct.h"
 #endif
-#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
+#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE)
 #include "hal/dedic_gpio_ll.h"
 #endif
 
@@ -50,11 +51,11 @@ struct dedic_gpio_platform_t {
     uint32_t in_occupied_mask;  // mask of input channels that already occupied
 #if SOC_DEDIC_GPIO_HAS_INTERRUPT
     intr_handle_t intr_hdl;     // interrupt handle
-    dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];   // array of callback function for input channel
-    void *cb_args[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];                   // array of callback arguments for input channel
-    dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel
+    dedic_gpio_isr_callback_t cbs[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)];   // array of callback function for input channel
+    void *cb_args[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)];                   // array of callback arguments for input channel
+    dedic_gpio_bundle_t *in_bundles[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel
 #endif
-#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS)
     dedic_dev_t *dev;
 #endif
 };
@@ -81,18 +82,18 @@ static esp_err_t dedic_gpio_build_platform(int core_id)
                 // initialize platform members
                 s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
                 // initial occupy_mask: 1111...100...0
-                s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1);
-                s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1);
-#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
+                s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1);
+                s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1);
+#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS)
                 s_platform[core_id]->dev = &DEDIC_GPIO;
-#endif // DEDIC_GPIO_LL_ALLOW_REG_ACCESS
-#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
+#endif // DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS)
+#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE)
                 // enable dedicated GPIO register clock
                 PERIPH_RCC_ATOMIC() {
                     dedic_gpio_ll_enable_bus_clock(true);
                     dedic_gpio_ll_reset_register();
                 }
-#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
+#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE)
             }
         }
         _lock_release(&s_platform_mutexlock[core_id]);
@@ -113,12 +114,12 @@ static void dedic_gpio_break_platform(int core_id)
         if (s_platform[core_id]) {
             free(s_platform[core_id]);
             s_platform[core_id] = NULL;
-#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
+#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE)
             // disable the register clock if no GPIO channel is in use
             PERIPH_RCC_ATOMIC() {
                 dedic_gpio_ll_enable_bus_clock(false);
             }
-#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
+#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE)
         }
         _lock_release(&s_platform_mutexlock[core_id]);
     }
@@ -222,11 +223,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
     // configure outwards channels
     uint32_t out_offset = 0;
     if (config->flags.out_en) {
-        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
-                          "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU));
+        ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
+                          "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU));
         // prevent install bundle concurrently
         portENTER_CRITICAL(&s_platform[core_id]->spinlock);
-        for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) - config->array_size; i++) {
+        for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - config->array_size; i++) {
             if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) {
                 out_mask = pattern << i;
                 out_offset = i;
@@ -235,7 +236,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
         }
         if (out_mask) {
             s_platform[core_id]->out_occupied_mask |= out_mask;
-#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS)
             // always enable instruction to access output GPIO, which has better performance than register access
             dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true);
 #endif
@@ -248,11 +249,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
     // configure inwards channels
     uint32_t in_offset = 0;
     if (config->flags.in_en) {
-        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
-                          "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU));
+        ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
+                          "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU));
         // prevent install bundle concurrently
         portENTER_CRITICAL(&s_platform[core_id]->spinlock);
-        for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU) - config->array_size; i++) {
+        for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - config->array_size; i++) {
             if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) {
                 in_mask = pattern << i;
                 in_offset = i;
@@ -320,8 +321,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
     portENTER_CRITICAL(&s_platform[core_id]->spinlock);
     s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);
     s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);
-    if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1)) &&
-            s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1))) {
+    if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1)) &&
+            s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1))) {
         recycle_all = true;
     }
     portEXIT_CRITICAL(&s_platform[core_id]->spinlock);

components/esp_driver_gpio/src/gpio.c

@@ -32,9 +32,12 @@ static const char *GPIO_TAG = "gpio";
 
 #define GPIO_ISR_CORE_ID_UNINIT    (3)
 
-//default value for SOC_GPIO_SUPPORT_RTC_INDEPENDENT is 0
-#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0
+// On ESP32, those PADs which have RTC functions must set pullup/down/drv capability via RTC register.
+// On other targets, digital IOs have their own registers to control pullup/down/drv capability, independent with RTC_IO (LP_IOMUX) registers.
+#if CONFIG_IDF_TARGET_ESP32
+#define GPIO_RTCIO_ARE_INDEPENDENT 0
+#else // for any other target has RTC_IO (LP_IOMUX) registers
+#define GPIO_RTCIO_ARE_INDEPENDENT 1
 #endif
 
 typedef struct {
@@ -77,7 +80,7 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -96,7 +99,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -115,7 +118,7 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -134,7 +137,7 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -701,7 +704,7 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng
     GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -722,7 +725,7 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
     GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -1062,7 +1065,7 @@ esp_err_t gpio_get_io_config(gpio_num_t gpio_num, gpio_io_config_t *out_io_confi
     ESP_RETURN_ON_FALSE(out_io_config, ESP_ERR_INVALID_ARG, GPIO_TAG, "out_io_config is a null pointer");
 
     gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, out_io_config);
-#if !SOC_GPIO_SUPPORT_RTC_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0
+#if !GPIO_RTCIO_ARE_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0
     if (rtc_gpio_is_valid_gpio(gpio_num)) {
         int rtcio_num = rtc_io_number_get(gpio_num);
         out_io_config->pu = rtcio_hal_is_pullup_enabled(rtcio_num);

components/esp_driver_gpio/src/gpio_etm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include "esp_log.h"
 #include "esp_check.h"
 #include "soc/soc_caps.h"
+#include "hal/gpio_caps.h"
 #include "hal/gpio_ll.h"
 #include "hal/gpio_etm_ll.h"
 #include "esp_private/etm_interface.h"
@@ -29,10 +30,10 @@ typedef struct gpio_etm_event_t gpio_etm_event_t;
 typedef struct gpio_etm_group_t {
     portMUX_TYPE spinlock;
     gpio_etm_dev_t *dev;
-    uint8_t tasks[GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP];           // Array of the acquired action masks in each GPIO ETM task channel
-    uint8_t events[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP];         // Array of the acquired event masks in each GPIO ETM event channel
+    uint8_t tasks[GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP)];           // Array of the acquired action masks in each GPIO ETM task channel
+    uint8_t events[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)];         // Array of the acquired event masks in each GPIO ETM event channel
     uint8_t actions[SOC_GPIO_PIN_COUNT];                          // Array of the masks of the added actions to each GPIO
-    uint8_t edges[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP];          // Array of the masks of the bound event edges in each GPIO ETM event channel
+    uint8_t edges[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)];          // Array of the masks of the bound event edges in each GPIO ETM event channel
 } gpio_etm_group_t;
 
 struct gpio_etm_event_t {
@@ -63,7 +64,7 @@ static esp_err_t gpio_etm_acquire_event_channel(uint8_t event_mask, int *chan_id
     int free_chan_id = -1;
     // loop to search free event channel in the group
     portENTER_CRITICAL(&group->spinlock);
-    for (int j = 0; j < GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP; j++) {
+    for (int j = 0; j < GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP); j++) {
         if (!group->events[j]) {
             free_chan_id = j;
             group->events[j] = event_mask;
@@ -94,7 +95,7 @@ static esp_err_t gpio_etm_acquire_task_channel(uint8_t task_mask, int *chan_id)
     int free_chan_id = -1;
     // loop to search free task channel in the group
     portENTER_CRITICAL(&group->spinlock);
-    for (int j = 0; j < GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP; j++) {
+    for (int j = 0; j < GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP); j++) {
         if (!group->tasks[j]) {
             free_chan_id = j;
             group->tasks[j] = task_mask;

components/esp_driver_gpio/src/gpio_pin_glitch_filter.c

@@ -12,6 +12,7 @@
 #include "hal/gpio_ll.h"
 #include "esp_clk_tree.h"
 #include "esp_private/io_mux.h"
+#include "hal/gpio_caps.h"
 
 static const char *TAG = "gpio-filter";
 
@@ -93,11 +94,11 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf
     // create pm lock according to different clock source
 #if CONFIG_PM_ENABLE
     esp_pm_lock_type_t lock_type = ESP_PM_NO_LIGHT_SLEEP;
-#if SOC_GPIO_FILTER_CLK_SUPPORT_APB
+#if GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB)
     if (config->clk_src == GLITCH_FILTER_CLK_SRC_APB) {
         lock_type = ESP_PM_APB_FREQ_MAX;
     }
-#endif // SOC_GPIO_FILTER_CLK_SUPPORT_APB
+#endif // GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB)
     sprintf(filter->pm_lock_name, "filter_io_%d", config->gpio_num); // e.g. filter_io_0
     ESP_GOTO_ON_ERROR(esp_pm_lock_create(lock_type, 0, filter->pm_lock_name, &filter->pm_lock),
                       err, TAG, "create pm_lock failed");

components/esp_driver_gpio/src/rtc_io.c

@@ -16,6 +16,9 @@
 #include "hal/rtc_io_hal.h"
 #include "hal/rtc_io_periph.h"
 #include "soc/soc_caps.h"
+#if SOC_RTCIO_PIN_COUNT > 0
+#include "hal/rtc_gpio_caps.h"
+#endif
 #if SOC_LP_GPIO_MATRIX_SUPPORTED
 #include "soc/lp_gpio_pins.h"
 #endif
@@ -263,11 +266,11 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
 esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
     ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
-#if !SOC_RTCIO_EDGE_WAKE_SUPPORTED
+#if !RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED)
     if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) {
         return ESP_ERR_INVALID_ARG; // Dont support this mode.
     }
-#endif //!SOC_RTCIO_EDGE_WAKE_SUPPORTED
+#endif //!RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED)
     RTCIO_ENTER_CRITICAL();
     rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type);
     RTCIO_EXIT_CRITICAL();

components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c

@@ -12,16 +12,17 @@
 #include "unity_test_utils.h"
 #include "esp_rom_sys.h"
 #include "soc/soc_caps_full.h"
+#include "hal/dedic_gpio_caps.h"
 #include "hal/dedic_gpio_periph.h"
 #include "hal/dedic_gpio_cpu_ll.h"
 #include "driver/gpio.h"
 #include "driver/dedic_gpio.h"
 
 TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]")
 {
-    const int test_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2] = {0};
-    const int test2_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2 + 1] = {0};
-    const int test3_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) + 1] = {0};
+    const int test_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2] = {0};
+    const int test2_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2 + 1] = {0};
+    const int test3_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) + 1] = {0};
     dedic_gpio_bundle_handle_t test_bundle, test_bundle2, test_bundle3 = NULL;
     dedic_gpio_bundle_config_t bundle_config = {
         .gpio_array = test_gpios,
@@ -48,7 +49,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]")
     TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, dedic_gpio_new_bundle(&bundle_config, &test_bundle), "create bundle with half channels failed");
     uint32_t mask = 0;
     TEST_ESP_OK(dedic_gpio_get_out_mask(test_bundle, &mask));
-    TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask");
+    TEST_ASSERT_EQUAL_MESSAGE((1 << (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask");
     TEST_ESP_OK(dedic_gpio_get_in_mask(test_bundle, &mask));
     TEST_ASSERT_EQUAL_MESSAGE(0, mask, "wrong in mask");