Merge branch 'refactor/esp_hal_parlio' into 'master'

feat(hal): graudate the parlio hal driver into a new component

Closes IDF-14099

See merge request espressif/esp-idf!43359

Author: L-KAYA

components/esp_driver_parlio/CMakeLists.txt

@@ -21,5 +21,6 @@ endif()
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${public_include}
                        PRIV_REQUIRES "${priv_requires}"
+                       REQUIRES esp_hal_parlio
                        LDFRAGMENTS "linker.lf"
                       )

components/esp_driver_parlio/linker.lf

@@ -33,8 +33,8 @@ entries:
         esp_dma_utils: esp_dma_split_rx_buffer_to_cache_aligned (noflash)
         esp_dma_utils: esp_dma_merge_aligned_rx_buffers (noflash)
 
-[mapping:parlio_driver_soc_periph]
-archive: libsoc.a
+[mapping:parlio_driver_hal_periph]
+archive: libesp_hal_parlio.a
 entries:
     if PARLIO_RX_ISR_HANDLER_IN_IRAM = y:
         parlio_periph: parlio_periph_signals  (noflash)

components/esp_driver_parlio/src/parlio_common.c

@@ -11,8 +11,8 @@
 
 typedef struct parlio_platform_t {
     _lock_t mutex;                             // platform level mutex lock
-    parlio_group_t *groups[SOC_PARLIO_GROUPS]; // array of parallel IO group instances
-    int group_ref_counts[SOC_PARLIO_GROUPS];   // reference count used to protect group install/uninstall
+    parlio_group_t *groups[PARLIO_LL_GET(INST_NUM)]; // array of parallel IO group instances
+    int group_ref_counts[PARLIO_LL_GET(INST_NUM)];   // reference count used to protect group install/uninstall
 } parlio_platform_t;
 
 static parlio_platform_t s_platform; // singleton platform
@@ -110,20 +110,20 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit)
 {
     parlio_group_t *group = NULL;
     int unit_id = -1;
-    for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
+    for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
         group = parlio_acquire_group_handle(i);
         ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no memory for group (%d)", i);
         portENTER_CRITICAL(&group->spinlock);
         if (unit->dir == PARLIO_DIR_TX) {
-            for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
+            for (int j = 0; j < PARLIO_LL_GET(TX_UNITS_PER_INST); j++) {
                 if (!group->tx_units[j]) {
                     group->tx_units[j] = unit;
                     unit_id = j;
                     break;
                 }
             }
         } else {
-            for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
+            for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
                 if (!group->rx_units[j]) {
                     group->rx_units[j] = unit;
                     unit_id = j;

components/esp_driver_parlio/src/parlio_priv.h

@@ -28,7 +28,7 @@
 #include "freertos/idf_additions.h"
 #include "soc/soc_caps.h"
 #include "soc/gdma_channel.h"
-#include "soc/parlio_periph.h"
+#include "hal/parlio_periph.h"
 #include "hal/parlio_types.h"
 #include "hal/parlio_hal.h"
 #include "hal/parlio_ll.h"
@@ -133,8 +133,8 @@ typedef struct parlio_group_t {
     portMUX_TYPE              spinlock;     // to protect per-group register level concurrent access
     parlio_hal_context_t      hal;          // hal layer context
     uint32_t                  dma_align;    // DMA buffer alignment
-    parlio_unit_base_handle_t    tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
-    parlio_unit_base_handle_t    rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP]; // rx unit handles
+    parlio_unit_base_handle_t    tx_units[PARLIO_LL_GET(TX_UNITS_PER_INST)]; // tx unit handles
+    parlio_unit_base_handle_t    rx_units[PARLIO_LL_GET(RX_UNITS_PER_INST)]; // rx unit handles
 } parlio_group_t;
 
 /**

components/esp_driver_parlio/src/parlio_rx.c

@@ -268,14 +268,14 @@ static esp_err_t parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, const
     /* When the source clock comes from internal and supported to output the internal clock,
      * enable the gpio output direction and connect to the clock output signal */
     if (config->clk_out_gpio_num >= 0) {
-#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
+#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
         gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
         // connect the signal to the GPIO by matrix, it will also enable the output path properly
         esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num,
                                         parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_out_sig, false, false);
 #else
         ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "this target not support to output the clock");
-#endif // SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
+#endif // PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
     }
 
     /* Initialize the valid GPIO as input */

components/esp_driver_parlio/src/parlio_tx.c

@@ -520,14 +520,14 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
         }
     } else {
         // non-loop transmission
-#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
         // for DMA EOF supported target, we need to set the EOF condition to DMA EOF
         parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF);
 #else
         // for DMA EOF not supported target, we need to set the bit length to the configured bit lens
         parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN);
         parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits);
-#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
     }
 
     if (tx_unit->bs_handle) {
@@ -641,9 +641,9 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
     ESP_RETURN_ON_FALSE(tx_unit && payload && payload_bits, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     ESP_RETURN_ON_FALSE((payload_bits % tx_unit->data_width) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must align to bus width");
     ESP_RETURN_ON_FALSE(payload_bits <= tx_unit->max_transfer_bits, ESP_ERR_INVALID_ARG, TAG, "payload bit length too large");
-#if !SOC_PARLIO_TRANS_BIT_ALIGN
+#if !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
     ESP_RETURN_ON_FALSE((payload_bits % 8) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must be multiple of 8");
-#endif // !SOC_PARLIO_TRANS_BIT_ALIGN
+#endif // !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
 
 #if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
     if (config->flags.loop_transmission) {
@@ -654,13 +654,13 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
     ESP_RETURN_ON_FALSE(config->flags.loop_transmission == false, ESP_ERR_NOT_SUPPORTED, TAG, "loop transmission is not supported on this chip");
 #endif
 
-#if !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#if !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
     // check the max payload size if it's not a loop transmission and the DMA EOF is not supported
     if (!config->flags.loop_transmission) {
         ESP_RETURN_ON_FALSE(tx_unit->max_transfer_bits <= PARLIO_LL_TX_MAX_BITS_PER_FRAME,
                             ESP_ERR_INVALID_ARG, TAG, "invalid transfer size, max transfer size should be less than %d", PARLIO_LL_TX_MAX_BITS_PER_FRAME / 8);
     }
-#endif // !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#endif // !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
 
     size_t alignment = esp_ptr_external_ram(payload) ? tx_unit->ext_mem_align : tx_unit->int_mem_align;
     // check alignment

components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt

@@ -9,16 +9,17 @@ project(parlio_test)
 
 idf_build_get_property(elf EXECUTABLE)
 if(CONFIG_COMPILER_DUMP_RTL_FILES)
-    add_custom_target(check_test_app_sections ALL
-                      COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
-                      --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,${CMAKE_BINARY_DIR}/esp-idf/hal/
-                      --elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
-                      find-refs
-                      --from-sections=.iram0.text
-                      --to-sections=.flash.text,.flash.rodata
-                      --exit-code
-                      DEPENDS ${elf}
-                      )
+    add_custom_target(
+        check_test_app_sections ALL
+        COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
+        --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio/
+        --elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
+        find-refs
+        --from-sections=.iram0.text
+        --to-sections=.flash.text,.flash.rodata
+        --exit-code
+        DEPENDS ${elf}
+    )
 endif()
 
 message(STATUS "Checking parlio registers are not read-write by half-word")

components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt

@@ -19,7 +19,7 @@ endif()
 idf_component_register(SRCS ${srcs}
                        PRIV_REQUIRES unity esp_driver_parlio esp_driver_gpio
                                     esp_driver_i2s esp_driver_spi esp_psram
-                                    esp_driver_bitscrambler
+                                    esp_driver_bitscrambler esp_hal_parlio
                        WHOLE_ARCHIVE)
 
 if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED)

components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c

@@ -202,7 +202,7 @@ TEST_CASE("parlio_tx_bitscrambler_test", "[parlio_bitscrambler]")
     test_parlio_bitscrambler();
 }
 
-#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
 static void test_parlio_bitscrambler_different_input_output_sizes(void)
 {
     parlio_tx_unit_handle_t tx_unit = NULL;
@@ -353,4 +353,4 @@ TEST_CASE("parlio_tx_bitscrambler_different_input_output_sizes_test", "[parlio_b
 {
     test_parlio_bitscrambler_different_input_output_sizes();
 }
-#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
+#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)

components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c

@@ -20,7 +20,8 @@
 #include "hal/cache_ll.h"
 #include "soc/soc_caps.h"
 #include "soc/spi_periph.h"
-#include "soc/parlio_periph.h"
+#include "hal/parlio_periph.h"
+#include "hal/parlio_ll.h"
 #include "esp_attr.h"
 #include "test_board.h"
 #include "esp_private/parlio_rx_private.h"
@@ -29,7 +30,7 @@
 #define TEST_I2S_PORT   I2S_NUM_0
 #define TEST_VALID_SIG  (PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1)
 
-#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
+#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
 #define TEST_OUTPUT_CLK_PIN     TEST_CLK_GPIO
 #else
 #define TEST_OUTPUT_CLK_PIN     -1
@@ -399,11 +400,11 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
 TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
 {
     printf("install rx units exhaustively\r\n");
-    parlio_rx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_RX_UNITS_PER_GROUP];
+    parlio_rx_unit_handle_t units[PARLIO_LL_GET(INST_NUM) * PARLIO_LL_GET(RX_UNITS_PER_INST)];
     int k = 0;
     parlio_rx_unit_config_t config = TEST_DEFAULT_UNIT_CONFIG(PARLIO_CLK_SRC_DEFAULT, 1000000);
-    for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
-        for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
+    for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
+        for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
             TEST_ESP_OK(parlio_new_rx_unit(&config, &units[k++]));
         }
     }
@@ -421,7 +422,7 @@ TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
     // clock from internal
     config.clk_src = PARLIO_CLK_SRC_DEFAULT;
     config.clk_out_gpio_num = TEST_CLK_GPIO;
-#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
+#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
     TEST_ESP_OK(parlio_new_rx_unit(&config, &units[0]));
     TEST_ESP_OK(parlio_del_rx_unit(units[0]));
 #else