rivierapro: Add VHDL generics support

Author: olofk

edalize/rivierapro.py

@@ -17,7 +17,7 @@
 
 class Rivierapro(Edatool):
 
-    argtypes = ["plusarg", "vlogdefine", "vlogparam"]
+    argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"]
 
     @classmethod
     def get_doc(cls, api_ver):
@@ -173,6 +173,8 @@ def _write_run_tcl_file(self):
         # Top-level parameters
         for key, value in self.vlogparam.items():
             args += ["-g{}={}".format(key, self._param_value_str(value))]
+        for key, value in self.generic.items():
+            args += ["-g{}={}".format(key, self._param_value_str(value))]
         tcl_launch.write(" ".join(args) + "\n")
         tcl_launch.close()
 

tests/test_rivierapro.py

@@ -11,7 +11,11 @@ def test_rivierapro(make_edalize_test):
     }
 
     # FIXME: Add VPI tests
-    tf = make_edalize_test("rivierapro", tool_options=tool_options)
+    tf = make_edalize_test(
+        "rivierapro",
+        tool_options=tool_options,
+        param_types=["plusarg", "vlogdefine", "vlogparam", "generic"],
+    )
     tf.backend.configure()
 
     tf.compare_files(

tests/test_rivierapro/edalize_launch.tcl

@@ -1 +1 @@
-vsim a few vsim_options top_module +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -gvlogparam_bool=1 -gvlogparam_int=42 -gvlogparam_str=hello
+vsim a few vsim_options top_module +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -gvlogparam_bool=1 -gvlogparam_int=42 -gvlogparam_str=hello -ggeneric_bool=1 -ggeneric_int=42 -ggeneric_str=hello