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Fixed workdir for ghdl in template creation
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+27
-13
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8 files changed

+27
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‎README.rst‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,6 @@ Tada! We have simulated. As an exercise, try to just change the tool variable to
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Now it's time to create an FPGA image instead
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139-
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As you have seen, Edalize is an award-winning tool for interfacing EDA tools, so
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**Edalize it, don't criticize it!**

‎edalize/ghdl.py‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ def configure_main(self):
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libraries = collections.OrderedDict()
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library_options = "--work={lib} --workdir=./{lib}"
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top_workdir_options = "--workdir=./{lib}"
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ghdlimport = ""
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vhdl_sources = ""
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@@ -114,6 +115,11 @@ def configure_main(self):
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libraries[top[0]] = []
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top_libraries = library_options.format(lib=top[0])
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top_workdir = ""
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if len(top) > 1:
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libraries[top[0]] = []
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top_workdir = top_workdir_options.format(lib=top[0])
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top_unit = top[-1]
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for f in src_files:
@@ -154,7 +160,7 @@ def configure_main(self):
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"run_options": " ".join(run_options),
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"make_libraries_directories": make_libraries_directories,
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"ghdlimport": ghdlimport,
157-
"top_libraries": top_libraries,
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"top_workdir": top_workdir,
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},
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)
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‎edalize/templates/ghdl/Makefile.j2‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ TOPLEVEL = {{ toplevel }}
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TOPLEVEL_LIBS = {{ top_libraries }}
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ANALYZE_OPTIONS = {{ analyze_options }}
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RUN_OPTIONS = {{ run_options }}
7-
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TOP_WORKDIR = {{ top_workdir }}
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VHDL_SOURCES = {{ vhdl_sources }}
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all: work-obj{{ standard }}.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
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$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
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$(TOPLEVEL): $(VHDL_SOURCES) work-obj{{ standard }}.cf
16-
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
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$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
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$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj{{ standard }}.cf
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$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

‎tests/edalize_common.py‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,12 @@
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import shutil
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import pytest
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import logging
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from edalize.edatool import get_edatool
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logger = logging.getLogger('Edalize')
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logger.setLevel (logging.INFO)
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tests_dir = os.path.dirname(__file__)
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@@ -136,9 +139,15 @@ def compare_files(ref_dir, work_root, files):
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if "GOLDEN_RUN" in os.environ:
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shutil.copy(generated_file, reference_file)
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with open(reference_file) as fref, open(generated_file) as fgen:
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assert fref.read() == fgen.read(), f
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if fref.read() != fgen.read():
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logger.info(f"{fref}")
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logger.info(f"{fgen}")
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with open(reference_file) as fref, open(generated_file) as fgen:
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assert fref.read() == fgen.read(), f
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def get_flow(name):
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return getattr(import_module("edalize.flows.{}".format(name)), name.capitalize())

‎tests/test_ghdl/test01/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
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TOPLEVEL_LIBS =
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ANALYZE_OPTIONS = some analyze_options -P./libx
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RUN_OPTIONS = a few run_options
7-
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TOP_WORKDIR =
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VHDL_SOURCES = vhdl_file.vhd vhdl_lfile vhdl2008_file
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all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
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$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
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$(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
16-
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
16+
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
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$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
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$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

‎tests/test_ghdl/test02/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
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TOPLEVEL_LIBS =
55
ANALYZE_OPTIONS = some analyze_options -P./libx
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RUN_OPTIONS = a few run_options
7-
7+
TOP_WORKDIR =
88
VHDL_SOURCES = vhdl_file.vhd vhdl_lfile
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all: work-obj93.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
1313
$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
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1515
$(TOPLEVEL): $(VHDL_SOURCES) work-obj93.cf
16-
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
16+
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
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$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj93.cf
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$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

‎tests/test_ghdl/test03/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
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TOPLEVEL_LIBS =
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ANALYZE_OPTIONS = --ieee=synopsys -P./libx
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RUN_OPTIONS = a few run_options
7-
7+
TOP_WORKDIR =
88
VHDL_SOURCES = vhdl_file.vhd vhdl_lfile
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all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
1313
$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
1414

1515
$(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
16-
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
16+
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
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1818
$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
1919
$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

‎tests/test_ghdl/test04/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ TOPLEVEL = vhdl_lfile
44
TOPLEVEL_LIBS = --work=libx --workdir=./libx
55
ANALYZE_OPTIONS = some analyze_options -P./libx
66
RUN_OPTIONS = a few run_options
7-
7+
TOP_WORKDIR = --workdir=./libx
88
VHDL_SOURCES = vhdl_file.vhd vhdl_lfile vhdl2008_file
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1010
all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
1313
$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
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$(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
16-
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
16+
$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
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1818
$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
1919
$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

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