With the way the current Makefile is written, Synthesis, Implementation, etc. are not re-run when a Verilog parameter is changed in the edam. This is because the .xpr file is an order-only prerequisite of the successive targets, and is the only file updated when the parameter is changed.

I'm really not a makefile expert. My gut tells me one of two solutions needs to be used here. One is having design-affecting parameters in their own .tcl file that is a normal prerequisite of the synth target (or have it be part of the existing _synth.tcl which is already a prerequisite there). The other is using some sort of phony target, but I can't quite see a justification for that when there is a material code change to prompt the rebuild.

I'd be willing to help with working towards a solution here, but I'm wondering if there aren't other gaps where changes in the design need to be added to this issue and we can try to solve them all at once.