Mismatch Between openofdm_rx Output and openofdm_tx Input in Simulation

[Tagabey]

Hello,
I performed a simulation of the openofdm_tx using the packet data from the file "ht_tx_intf_mem_mcs7_gi1_aggr0_byte100.mem". Then, I simulated the openofdm_rx path using the I/Q samples generated from the TX output as input.

After the simulation, I compared the contents of byte_out.txt (the output bytes from the openofdm_rx) with the original bit source file used as input to the openofdm_tx. I noticed that the two files do not match.

Is there anything incorrect or missing in my simulation workflow that could explain this mismatch?

[Szum123321]

The first two words appear to be a configuration data for the transmitter so a mismatch there is expected.
Here's the verilog file where it is decoded

And this is my best attempt to convert the logic into a usable C struct a that describes well the format.

struct __attribute__((packed)) openofdm_tx_header {
	// First word
	uint8_t legacy_rate : 4;
	uint8_t padding1 : 1;
	uint16_t legacy_byte_count : 12; // Can safely be ignored when in HT-mode
	uint8_t padding2 : 7;
	uint8_t ht_flag : 1;
	uint64_t padding3 : 39; // Pad to 64-bits/first buffer word

	uint8_t ht_rate : 3;
	uint16_t padding4 : 5;
	uint16_t ht_byte_count : 16;
	uint8_t padding5 : 3;
	uint8_t ht_aggregate : 1;
	uint8_t padding6 : 3;
	uint8_t short_guard_interval : 1;
	uint32_t padding7;
};