Instrumentation: Stabilize DMM trigger timing for fast phase sweep plateaus #12
Description
Context
Source: session recap email (2026-02-19)
Problem
Communication/delay reduction lowered phase sweep plateaus from 400 ms to 5 ms, but DMM DC current acquisition became fragile due to jitter on external trigger and poor control of some measurement timings.
Expected Outcome
A deterministic timing/trigger strategy keeps measurement stability at short plateaus and documents operating limits.
Scope
In:
- Characterize trigger jitter and timing uncertainty on DMM path.
- Define safe timing budget for 5-10 ms plateaus.
- Update measurement sequence/timing controls to ensure stable DC current reading.
Out: - Reverting optimization to 400 ms plateaus by default.
- Hardware redesign of DMM setup.
Acceptance Criteria
- Timing diagram of trigger/measurement sequence is documented.
- DC current measurement repeatability is validated at reduced plateau durations.
- Recommended timing parameters are documented and applied.
Evidence / Notes
- Email excerpt: "paliers ... réduit à 5ms ... mesure de courant DC avec les DMM devient + critique ... jitter ... non maitrise de certains temps de mesure"
- Related files/paths:
supervisor_v2_2.py,comm_protocol/ - Related issue(s): none