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Merge pull request #54 from quartiq/test-lowpass
benchmark: enable semihosting, try qemu
2 parents 16f3ae8 + 95c2970 commit 9e172a0

6 files changed

Lines changed: 19 additions & 6 deletions

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tests/embedded/.cargo/config.toml

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@@ -2,6 +2,10 @@
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runner = "probe-rs run --chip STM32H743ZITx"
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rustflags = ["-C", "target-cpu=cortex-m7"]
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[target.thumbv7m-none-eabi]
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runner = "./qemu.sh"
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rustflags = ["-C", "target-cpu=cortex-m7"]
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[build]
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target = "thumbv7em-none-eabihf"
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tests/embedded/Cargo.toml

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@@ -8,11 +8,14 @@ publish = false
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[workspace]
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[dependencies]
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defmt = "1.0.1"
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defmt-rtt = "1.0.0"
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cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
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cortex-m-rt = { version = "0.7.0", default-features = false }
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panic-probe = { version = "1.0.0", features = ["print-defmt"] }
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defmt = "1.0.1"
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defmt-rtt = { version = "1.0.0", optional = true }
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defmt-semihosting = { version = "0.3.0", optional = true }
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panic-probe = { version = "1.0.0", features = ["print-defmt"], optional = true }
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panic-semihosting = { version = "0.6.0", optional = true }
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cortex-m-semihosting = { version = "0.5", optional = true }
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idsp = { version = "0.21", path = "../.." }
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dsp-process = { version = "0.2", path = "../../dsp-process" }
@@ -31,3 +34,8 @@ codegen-units = 1
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incremental = false
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lto = true
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opt-level = 2
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[features]
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rtt = ["dep:defmt-rtt", "dep:panic-probe"]
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semihosting = ["dep:defmt-semihosting", "dep:panic-semihosting", "dep:cortex-m-semihosting"]
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default = ["rtt"]

tests/embedded/src/bin/biquad.rs

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@@ -4,7 +4,6 @@
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use cortex_m::asm;
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use defmt::*;
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use num_traits::Float;
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use {defmt_rtt as _, panic_probe as _};
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use dsp_fixedpoint::Q32;
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use dsp_process::{Add, Identity, Pair, Parallel, Unsplit};

tests/embedded/src/bin/hbf.rs

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@@ -5,7 +5,6 @@ use core::hint::black_box;
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use cortex_m::asm;
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use defmt::*;
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use {defmt_rtt as _, panic_probe as _};
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use dsp_process::{FnProcess, Split};
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use idsp::hbf;

tests/embedded/src/bin/trig.rs

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@@ -3,14 +3,14 @@
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use cortex_m::asm;
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use defmt::*;
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use {defmt_rtt as _, panic_probe as _};
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use dsp_process::FnProcess;
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use idsp_embedded_bench::*;
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#[cortex_m_rt::entry]
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fn main() -> ! {
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info!("Setup");
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let mut c = unwrap!(cortex_m::Peripherals::take());
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// c.SCB.enable_icache();

tests/embedded/src/lib.rs

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@@ -7,7 +7,10 @@ use core::{
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};
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use cortex_m::peripheral::DWT;
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use defmt::*;
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#[cfg(feature = "rtt")]
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use {defmt_rtt as _, panic_probe as _};
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#[cfg(feature = "semihosting")]
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use {defmt_semihosting as _, panic_semihosting as _};
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use dsp_process::{Inplace, Process};
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