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MdePkg: Add PCIe capability structures for DPC and DLF
Add definitions for Downstream Port Containment (DPC) Extended Capability. Add definitions for Data Link Feature (DLF). Update existing definitions for Precision Time Measurement (PTM) and move it from PciExpress40.h to PciExpress31.h as it was defined in 3.1. Update existing definitions for Process Address Space ID (PASID) and move it to top of file to follow ID order. Mark some duplicate symbols 'obsolete' to remove in future. Signed-off-by: Jacek Kolakowski <[email protected]>
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‎MdePkg/Include/IndustryStandard/Pci30.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,11 @@
3939
**/
4040
#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
4141

42-
///
43-
/// PCI Capability List IDs and records
44-
///
42+
//
43+
// Symbol EFI_PCI_CAPABILITY_ID_PCIEXP is obsolete, use PCI_EXPRESS_CAPABILITY_ID.
44+
// PCI_EXPRESS_CAPABILITY_ID is defined beside the capability registers structure
45+
// in PciExpress21.h. This ID is not EFI nor PCI symbol, but PCI Express.
46+
//
4547
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
4648

4749
#pragma pack(1)

‎MdePkg/Include/IndustryStandard/PciExpress21.h‎

Lines changed: 42 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,17 @@
3030
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
3131

3232
#pragma pack(1)
33-
///
34-
/// PCI Express Capability Structure
35-
///
33+
34+
//
35+
// PCI Express Capability Structure version 2.
36+
// Mandatory for PCI Express devices. If not present it is not PCI Express device, thus no extended config space.
37+
// Version 1 ends at PCI_CAPABILITY_PCIEXP::RootStatus register.
38+
// Version 2 extends version 1 up to PCI_CAPABILITY_PCIEXP::SlotStatus2 register.
39+
//
40+
#define PCI_EXPRESS_CAPABILITY_ID 0x0010
41+
#define PCI_EXPRESS_CAPABILITY_VER1 0x1
42+
#define PCI_EXPRESS_CAPABILITY_VER2 0x2
43+
3644
typedef union {
3745
struct {
3846
UINT16 Version : 4;
@@ -396,29 +404,29 @@ typedef union {
396404
} PCI_REG_PCIE_SLOT_CAPABILITY2;
397405

398406
typedef struct {
399-
EFI_PCI_CAPABILITY_HDR Hdr;
400-
PCI_REG_PCIE_CAPABILITY Capability;
401-
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
402-
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
403-
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
404-
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
405-
PCI_REG_PCIE_LINK_CONTROL LinkControl;
406-
PCI_REG_PCIE_LINK_STATUS LinkStatus;
407-
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
408-
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
409-
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
410-
PCI_REG_PCIE_ROOT_CONTROL RootControl;
411-
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
412-
PCI_REG_PCIE_ROOT_STATUS RootStatus;
413-
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
414-
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
415-
UINT16 DeviceStatus2;
416-
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
417-
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
418-
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
419-
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
420-
UINT16 SlotControl2;
421-
UINT16 SlotStatus2;
407+
EFI_PCI_CAPABILITY_HDR Hdr; // Offset 00 size 2
408+
PCI_REG_PCIE_CAPABILITY Capability; // Offset 02 size 2
409+
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; // Offset 04 size 4
410+
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; // Offset 08 size 2
411+
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; // Offset 0A size 2
412+
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; // Offset 0C size 4
413+
PCI_REG_PCIE_LINK_CONTROL LinkControl; // Offset 10 size 2
414+
PCI_REG_PCIE_LINK_STATUS LinkStatus; // Offset 12 size 2
415+
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; // Offset 14 size 4
416+
PCI_REG_PCIE_SLOT_CONTROL SlotControl; // Offset 18 size 2
417+
PCI_REG_PCIE_SLOT_STATUS SlotStatus; // Offset 1A size 2
418+
PCI_REG_PCIE_ROOT_CONTROL RootControl; // Offset 1C size 2
419+
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; // Offset 1E size 2
420+
PCI_REG_PCIE_ROOT_STATUS RootStatus; // Offset 20 size 4 - Ver1 ends here
421+
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; // Offset 24 size 4
422+
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; // Offset 28 size 2
423+
UINT16 DeviceStatus2; // Offset 2A size 2
424+
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; // Offset 2C size 4
425+
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; // Offset 30 size 2
426+
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; // Offset 32 size 2
427+
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2; // Offset 34 size 4
428+
UINT16 SlotControl2; // Offset 38 size 2
429+
UINT16 SlotStatus2; // Offset 3A size 2
422430
} PCI_CAPABILITY_PCIEXP;
423431

424432
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
@@ -429,12 +437,12 @@ typedef struct {
429437
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
430438

431439
//
432-
// for SR-IOV
440+
// Single Root IO Virtualization (SR-IOV) Extended Capability Structure.
433441
//
434-
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
435-
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
436-
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
437-
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
442+
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E // Obsolete, use PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
443+
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F // Obsolete, use PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID
444+
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10 // Obsolete, use PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID
445+
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11 // Obsolete, deprecated in 6.0
438446

439447
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID 0x0010
440448
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_VER1 0x1
@@ -739,10 +747,9 @@ typedef struct {
739747

740748
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
741749

742-
/// Address Translation Services Extended Capability Structure
743-
///
744-
/// Based on section 5.1 of PCI Express Address Translation Services Specification 1.1
745-
///@{
750+
//
751+
// Address Translation Services (ATS) Extended Capability Structure.
752+
//
746753
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID 0x000F
747754
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_VER1 0x1
748755

@@ -770,7 +777,6 @@ typedef struct {
770777
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY Capability;
771778
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL Control;
772779
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS;
773-
///@}
774780

775781
#pragma pack()
776782

‎MdePkg/Include/IndustryStandard/PciExpress31.h‎

Lines changed: 129 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,110 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
1515

1616
#pragma pack(1)
1717

18+
//
19+
// Process Address Space ID (PASID) Extended Capability Structure.
20+
//
21+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B
22+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1
23+
24+
typedef union {
25+
struct {
26+
UINT16 Reserved0 : 1; // [0]
27+
UINT16 ExecutePermissionSupport : 1; // [1]
28+
UINT16 PrivilegedModeSupport : 1; // [2]
29+
UINT16 TranslatedReqWithPasidSupport : 1; // [3]
30+
UINT16 Reserved1 : 3; // [7:4]
31+
UINT16 MaxPasidWidth : 5; // [12:8]
32+
UINT16 Reserved2 : 3; // [15:13]
33+
} Bits;
34+
UINT16 Uint16;
35+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY;
36+
37+
typedef union {
38+
struct {
39+
UINT16 PasidEnable : 1; // [0]
40+
UINT16 ExecutePermissionEnable : 1; // [1]
41+
UINT16 PrivilegedModeEnable : 1; // [2]
42+
UINT16 TranslatedReqWithPasidEnable : 1; // [3]
43+
UINT16 Reserved : 12;
44+
} Bits;
45+
UINT16 Uint16;
46+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL;
47+
48+
typedef struct {
49+
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
50+
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability;
51+
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control;
52+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID;
53+
54+
//
55+
// Downstream Port Containment (DPC) Extended Capability.
56+
//
57+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DPC_ID 0x001D
58+
59+
typedef union {
60+
struct {
61+
UINT16 DpcInterruptMsgNo : 5; // [4:0]
62+
UINT16 RpExtensionsForDpc : 1; // [5]
63+
UINT16 PoisonedTlpEgressBlockingSupp : 1; // [6]
64+
UINT16 DpcSoftwareTriggerSupp : 1; // [7]
65+
UINT16 RpPioLogSize : 4; // [11:8] Bits [3:0] of log size
66+
UINT16 DlActiveErrCorSignalingSupp : 1; // [12]
67+
UINT16 RpPioLogSizeExt : 1; // [13] Bit [4] of log size
68+
UINT16 Reserved : 2; // [15:14]
69+
} Bits;
70+
UINT32 Uint16;
71+
} PCI_EXPRESS_REG_DPC_CAPABILITY;
72+
73+
typedef union {
74+
struct {
75+
UINT16 DpcTriggerEn : 2; // [1:0]
76+
UINT16 DpcCompletionCtl : 1; // [2]
77+
UINT16 DpcInterruptEn : 1; // [3]
78+
UINT16 DpcErrCorEn : 1; // [4]
79+
UINT16 PoisonedTlpEgressBlockingEn : 1; // [5]
80+
UINT16 DpcSoftwareTrigger : 1; // [6]
81+
UINT16 DlActiveErrCorEn : 1; // [7]
82+
UINT16 DpcSigSfwEn : 1; // [8]
83+
UINT16 Reserved : 7; // [15:9]
84+
} Bits;
85+
UINT16 Uint16;
86+
} PCI_EXPRESS_REG_DPC_CONTROL;
87+
88+
typedef union {
89+
struct {
90+
UINT16 DpcTriggerStatus : 1; // [0]
91+
UINT16 DpcTriggerReason : 2; // [2:1]
92+
UINT16 DpcInterruptStatus : 1; // [3]
93+
UINT16 DpcRpBusy : 1; // [4]
94+
UINT16 DpcTriggerReasonExtension : 2; // [6:5]
95+
UINT16 Reserved0 : 1; // [7]
96+
UINT16 RpPioFirstErrorPointer : 5; // [12:8]
97+
UINT16 DpcSigSfwStatus : 1; // [13]
98+
UINT16 Reserved1 : 2; // [15:14]
99+
} Bits;
100+
UINT16 Uint16;
101+
} PCI_EXPRESS_REG_DPC_STATUS;
102+
103+
typedef struct {
104+
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
105+
PCI_EXPRESS_REG_DPC_CAPABILITY Capability; // Offset 04h size 2
106+
PCI_EXPRESS_REG_DPC_CONTROL Control; // Offset 06h size 2
107+
PCI_EXPRESS_REG_DPC_STATUS Status; // Offset 08h size 2
108+
UINT16 ErrSourceId; // Offset 0Ah size 2
109+
UINT32 RpPioStatus; // Offset 0Ch size 4
110+
UINT32 RpPioMask; // Offset 10h size 4
111+
UINT32 RpPioSeverity; // Offset 14h size 4
112+
UINT32 RpPioSysErr; // Offset 18h size 4
113+
UINT32 RpPioException; // Offset 1Ch size 4
114+
UINT32 RpPioHdrLog[4]; // Offset 20h size 16 header log DW 1-4
115+
UINT32 RpPioImpSpecLog; // Offset 30h size 4
116+
UINT32 RpPioHdrLogExt[10]; // Offset 34h size 40 header log DW 5-14
117+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DPC;
118+
119+
//
120+
// L1 PM Substates Extended Capability.
121+
//
18122
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
19123
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1
20124

@@ -67,41 +171,41 @@ typedef struct {
67171
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
68172
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
69173

70-
/// Process Address Space ID Extended Capability Structure
71-
///
72-
/// Based on section 7.29 of PCI Express Base Specification 3.1
73-
///@{
74-
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B
75-
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1
174+
//
175+
// Precision Time Measurement (PTM) Extended Capability.
176+
//
177+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PTM_ID 0x001F
76178

77179
typedef union {
78180
struct {
79-
UINT16 PasidSupport : 1;
80-
UINT16 ExecutePermissionSupport : 1;
81-
UINT16 PrivilegedModeSupport : 1;
82-
UINT16 Reserved1 : 5;
83-
UINT16 MaxPasidWidth : 5;
84-
UINT16 Reserved2 : 3;
181+
UINT32 PtmRequesterCapable : 1; // [0]
182+
UINT32 PtrmResponderCapable : 1; // [1]
183+
UINT32 PtmRootCapable : 1; // [2]
184+
UINT32 EPtmCapable : 1; // [3]
185+
UINT32 PtmPropatagionDelayAdaptCapable : 1; // [4]
186+
UINT32 Reserved0 : 3; // [7:5]
187+
UINT32 LocalClockGranularity : 8; // [15:8]
188+
UINT32 Reserved1 : 16; // [31:16]
85189
} Bits;
86-
UINT16 Uint16;
87-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY;
190+
UINT32 Uint32;
191+
} PCI_EXPRESS_REG_PTM_CAPABILITY;
88192

89193
typedef union {
90194
struct {
91-
UINT16 PasidEnable : 1;
92-
UINT16 ExecutePermissionEnable : 1;
93-
UINT16 PrivilegedModeEnable : 1;
94-
UINT16 Reserved : 13;
195+
UINT32 PtmEnable : 1; // [0]
196+
UINT32 RootSelect : 1; // [1]
197+
UINT32 Reserved0 : 6; // [7:2]
198+
UINT32 EffectiveGranularity : 8; // [15:8]
199+
UINT32 Reserved1 : 16; // [31:16]
95200
} Bits;
96-
UINT16 Uint16;
97-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL;
201+
UINT32 Uint32;
202+
} PCI_EXPRESS_REG_PTM_CONTROL;
98203

99204
typedef struct {
100-
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
101-
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability;
102-
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control;
103-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID;
104-
///@}
205+
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
206+
PCI_EXPRESS_REG_PTM_CAPABILITY Capability; // Offset 04h size 4
207+
PCI_EXPRESS_REG_PTM_CONTROL Control; // Offset 08h size 4
208+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM;
105209

106210
#pragma pack()
107211

‎MdePkg/Include/IndustryStandard/PciExpress40.h‎

Lines changed: 24 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -16,47 +16,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
1616

1717
#pragma pack(1)
1818

19-
/// Precision Time Management Extended Capability definitions.
20-
///
21-
/// Based on section 7.9.16 of PCI Express Base Specification 4.0.
22-
///@{
23-
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PTM_ID 0x001F
24-
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PTM_VER1 0x1
25-
26-
#define PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY_OFFSET 0x04
27-
#define PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL_OFFSET 0x08
19+
//
20+
// Data Link Feature (DLF) Extended Capability.
21+
//
22+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DLF_ID 0x0025
2823

2924
typedef union {
3025
struct {
31-
UINT32 PTMRequesterCapable : 1;
32-
UINT32 PTMResponderCapable : 1;
33-
UINT32 PTMRootCapable : 1;
34-
UINT32 ePTMCapable : 1;
35-
UINT32 PTMPropagationDelayAdaptationCapable : 1;
36-
UINT32 Reserved : 3;
37-
UINT32 LocalClockGranularity : 8;
38-
UINT32 Reserved2 : 16;
26+
UINT32 LocalScaledFlowControlSupported : 1; // [0]
27+
UINT32 LocalImmediateReadiness : 1; // [1]
28+
UINT32 LocalExtendedVcCount : 3; // [4:2]
29+
UINT32 LocalL0pExitLatency : 3; // [7:5]
30+
UINT32 Reserved0 : 15; // [22:8]
31+
UINT32 Reserved1 : 8; // [30:23]
32+
UINT32 DataLinkFeatureExchangeEnable : 1; // [31]
3933
} Bits;
4034
UINT32 Uint32;
41-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY;
35+
} PCI_EXPRESS_REG_DLF_CAPABILITY;
4236

4337
typedef union {
4438
struct {
45-
UINT32 PTMEnable : 1;
46-
UINT32 RootSelect : 1;
47-
UINT32 Reserved : 6;
48-
UINT32 EffectiveGranularity : 8;
49-
UINT32 Reserved2 : 16;
39+
UINT32 RemoteScaledFlowControlSupported : 1; // [0]
40+
UINT32 RemoteImmediateReadiness : 1; // [1]
41+
UINT32 ExtendedVcCound : 3; // [4:2]
42+
UINT32 RemoteL0pExitLatency : 3; // [7:5]
43+
UINT32 Reserved0 : 15; // [22:8]
44+
UINT32 Reserved1 : 8; // [30:23]
45+
UINT32 DataLinkFeatureStatusValid : 1; // [31]
5046
} Bits;
5147
UINT32 Uint32;
52-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL;
48+
} PCI_EXPRESS_REG_DLF_STATUS;
5349

5450
typedef struct {
55-
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
56-
PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY Capability;
57-
PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL Control;
58-
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM;
59-
///@}
51+
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
52+
PCI_EXPRESS_REG_DLF_CAPABILITY Capability;
53+
PCI_EXPRESS_REG_DLF_STATUS Status;
54+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DLF;
6055

6156
/// The Physical Layer PCI Express Extended Capability definitions.
6257
///

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