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MdeModulePkg,MdePkg: Add PCIe capability structures for DPC and DLF
Add definitions for Downstream Port Containment (DPC) Extended Capability. Add definitions for Data Link Feature (DLF). Update existing definitions for Process Address Space ID (PASID). Update existing definitions for Precision Time Measurement (PTM). Mark some duplicate symbols 'obsolete' to remove it in future. Remove MR-IOV symbols as MR-IOV has been deprecated in PCIe 6.0. Signed-off-by: Jacek Kolakowski <[email protected]>
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6 files changed

+190
-91
lines changed

6 files changed

+190
-91
lines changed

‎MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@ typedef struct _PCI_BAR PCI_BAR;
5151

5252
#define EFI_PCI_IOV_POLICY_ARI 0x0001
5353
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
54-
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
5554

5655
typedef enum {
5756
PciBarTypeUnknown = 0,
@@ -269,7 +268,6 @@ struct _PCI_IO_DEVICE {
269268
UINT8 PciExpressCapabilityOffset;
270269
UINT32 AriCapabilityOffset;
271270
UINT32 SrIovCapabilityOffset;
272-
UINT32 MrIovCapabilityOffset;
273271
PCI_BAR VfPciBar[PCI_MAX_BAR];
274272
UINT32 SystemPageSize;
275273
UINT16 InitialVFs;

‎MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2460,18 +2460,6 @@ CreatePciIoDevice (
24602460
}
24612461
}
24622462

2463-
if (PcdGetBool (PcdMrIovSupport)) {
2464-
Status = LocatePciExpressCapabilityRegBlock (
2465-
PciIoDevice,
2466-
EFI_PCIE_CAPABILITY_ID_MRIOV,
2467-
&PciIoDevice->MrIovCapabilityOffset,
2468-
NULL
2469-
);
2470-
if (!EFI_ERROR (Status)) {
2471-
DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
2472-
}
2473-
}
2474-
24752463
PciIoDevice->ResizableBarOffset = 0;
24762464
if (PcdGetBool (PcdPcieResizableBarSupport)) {
24772465
Status = LocatePciExpressCapabilityRegBlock (

‎MdePkg/Include/IndustryStandard/Pci30.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,11 @@
3939
**/
4040
#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
4141

42-
///
43-
/// PCI Capability List IDs and records
44-
///
42+
//
43+
// Symbol EFI_PCI_CAPABILITY_ID_PCIEXP is obsolete, use PCI_EXPRESS_CAPABILITY_ID.
44+
// PCI_EXPRESS_CAPABILITY_ID is defined beside the capability registers structure
45+
// in PciExpress21.h. This ID is not EFI nor PCI symbol, but PCI Express.
46+
//
4547
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
4648

4749
#pragma pack(1)

‎MdePkg/Include/IndustryStandard/PciExpress21.h‎

Lines changed: 47 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,17 @@
3030
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
3131

3232
#pragma pack(1)
33-
///
34-
/// PCI Express Capability Structure
35-
///
33+
34+
//
35+
// PCI Express Capability Structure version 2.
36+
// Mandatory for PCI Express devices. If not present it is not PCI Express device, thus no extended config space.
37+
// Version 1 ends at PCI_CAPABILITY_PCIEXP::RootStatus register.
38+
// Version 2 extends version 1 up to PCI_CAPABILITY_PCIEXP::SlotStatus2 register.
39+
//
40+
#define PCI_EXPRESS_CAPABILITY_ID 0x0010
41+
#define PCI_EXPRESS_CAPABILITY_VER1 0x1
42+
#define PCI_EXPRESS_CAPABILITY_VER2 0x2
43+
3644
typedef union {
3745
struct {
3846
UINT16 Version : 4;
@@ -396,29 +404,29 @@ typedef union {
396404
} PCI_REG_PCIE_SLOT_CAPABILITY2;
397405

398406
typedef struct {
399-
EFI_PCI_CAPABILITY_HDR Hdr;
400-
PCI_REG_PCIE_CAPABILITY Capability;
401-
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
402-
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
403-
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
404-
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
405-
PCI_REG_PCIE_LINK_CONTROL LinkControl;
406-
PCI_REG_PCIE_LINK_STATUS LinkStatus;
407-
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
408-
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
409-
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
410-
PCI_REG_PCIE_ROOT_CONTROL RootControl;
411-
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
412-
PCI_REG_PCIE_ROOT_STATUS RootStatus;
413-
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
414-
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
415-
UINT16 DeviceStatus2;
416-
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
417-
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
418-
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
419-
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
420-
UINT16 SlotControl2;
421-
UINT16 SlotStatus2;
407+
EFI_PCI_CAPABILITY_HDR Hdr; // Offset 00 size 2
408+
PCI_REG_PCIE_CAPABILITY Capability; // Offset 02 size 2
409+
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; // Offset 04 size 4
410+
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; // Offset 08 size 2
411+
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; // Offset 0A size 2
412+
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; // Offset 0C size 4
413+
PCI_REG_PCIE_LINK_CONTROL LinkControl; // Offset 10 size 2
414+
PCI_REG_PCIE_LINK_STATUS LinkStatus; // Offset 12 size 2
415+
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; // Offset 14 size 4
416+
PCI_REG_PCIE_SLOT_CONTROL SlotControl; // Offset 18 size 2
417+
PCI_REG_PCIE_SLOT_STATUS SlotStatus; // Offset 1A size 2
418+
PCI_REG_PCIE_ROOT_CONTROL RootControl; // Offset 1C size 2
419+
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; // Offset 1E size 2
420+
PCI_REG_PCIE_ROOT_STATUS RootStatus; // Offset 20 size 4 - Ver1 ends here
421+
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; // Offset 24 size 4
422+
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; // Offset 28 size 2
423+
UINT16 DeviceStatus2; // Offset 2A size 2
424+
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; // Offset 2C size 4
425+
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; // Offset 30 size 2
426+
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; // Offset 32 size 2
427+
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2; // Offset 34 size 4
428+
UINT16 SlotControl2; // Offset 38 size 2
429+
UINT16 SlotStatus2; // Offset 3A size 2
422430
} PCI_CAPABILITY_PCIEXP;
423431

424432
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
@@ -429,13 +437,18 @@ typedef struct {
429437
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
430438

431439
//
432-
// for SR-IOV
440+
// Definitions EFI_PCIE_CAPABILITY_ID_ARI, EFI_PCIE_CAPABILITY_ID_ATS, EFI_PCIE_CAPABILITY_ID_SRIOV,
441+
// are obsolete, will be removed in future. Instead use PCI Express definitions
442+
// PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID, PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID,
443+
// PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID.
433444
//
434-
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
435-
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
436-
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
437-
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
445+
#define EFI_PCIE_CAPABILITY_ID_ARI PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
446+
#define EFI_PCIE_CAPABILITY_ID_ATS PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID
447+
#define EFI_PCIE_CAPABILITY_ID_SRIOV PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID
438448

449+
//
450+
// Single Root IO Virtualization (SR-IOV) Extended Capability Structure.
451+
//
439452
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID 0x0010
440453
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_VER1 0x1
441454

@@ -739,10 +752,9 @@ typedef struct {
739752

740753
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
741754

742-
/// Address Translation Services Extended Capability Structure
743-
///
744-
/// Based on section 5.1 of PCI Express Address Translation Services Specification 1.1
745-
///@{
755+
//
756+
// Address Translation Services (ATS) Extended Capability Structure.
757+
//
746758
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID 0x000F
747759
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_VER1 0x1
748760

@@ -770,7 +782,6 @@ typedef struct {
770782
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY Capability;
771783
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL Control;
772784
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS;
773-
///@}
774785

775786
#pragma pack()
776787

‎MdePkg/Include/IndustryStandard/PciExpress31.h‎

Lines changed: 83 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,74 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
1515

1616
#pragma pack(1)
1717

18+
//
19+
// Downstream Port Containment (DPC) Extended Capability.
20+
//
21+
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DPC_ID 0x001D
22+
23+
typedef union {
24+
struct {
25+
UINT16 DpcInterruptMsgNo : 5; // [4:0]
26+
UINT16 RpExtensionsForDpc : 1; // [5]
27+
UINT16 PoisonedTlpEgressBlockingSupp : 1; // [6]
28+
UINT16 DpcSoftwareTriggerSupp : 1; // [7]
29+
UINT16 RpPioLogSize : 4; // [11:8] Bits [3:0] of log size
30+
UINT16 DlActiveErrCorSignalingSupp : 1; // [12]
31+
UINT16 RpPioLogSizeExt : 1; // [13] Bit [4] of log size
32+
UINT16 Reserved : 2; // [15:14]
33+
} Bits;
34+
UINT32 Uint16;
35+
} PCI_EXPRESS_REG_DPC_CAPABILITY;
36+
37+
typedef union {
38+
struct {
39+
UINT16 DpcTriggerEn : 2; // [1:0]
40+
UINT16 DpcCompletionCtl : 1; // [2]
41+
UINT16 DpcInterruptEn : 1; // [3]
42+
UINT16 DpcErrCorEn : 1; // [4]
43+
UINT16 PoisonedTlpEgressBlockingEn : 1; // [5]
44+
UINT16 DpcSoftwareTrigger : 1; // [6]
45+
UINT16 DlActiveErrCorEn : 1; // [7]
46+
UINT16 DpcSigSfwEn : 1; // [8]
47+
UINT16 Reserved : 7; // [15:9]
48+
} Bits;
49+
UINT16 Uint16;
50+
} PCI_EXPRESS_REG_DPC_CONTROL;
51+
52+
typedef union {
53+
struct {
54+
UINT16 DpcTriggerStatus : 1; // [0]
55+
UINT16 DpcTriggerReason : 2; // [2:1]
56+
UINT16 DpcInterruptStatus : 1; // [3]
57+
UINT16 DpcRpBusy : 1; // [4]
58+
UINT16 DpcTriggerReasonExtension : 2; // [6:5]
59+
UINT16 Reserved0 : 1; // [7]
60+
UINT16 RpPioFirstErrorPointer : 5; // [12:8]
61+
UINT16 DpcSigSfwStatus : 1; // [13]
62+
UINT16 Reserved1 : 2; // [15:14]
63+
} Bits;
64+
UINT16 Uint16;
65+
} PCI_EXPRESS_REG_DPC_STATUS;
66+
67+
typedef struct {
68+
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
69+
PCI_EXPRESS_REG_DPC_CAPABILITY Capability; // Offset 04h size 2
70+
PCI_EXPRESS_REG_DPC_CONTROL Control; // Offset 06h size 2
71+
PCI_EXPRESS_REG_DPC_STATUS Status; // Offset 08h size 2
72+
UINT16 ErrSourceId; // Offset 0Ah size 2
73+
UINT32 RpPioStatus; // Offset 0Ch size 4
74+
UINT32 RpPioMask; // Offset 10h size 4
75+
UINT32 RpPioSeverity; // Offset 14h size 4
76+
UINT32 RpPioSysErr; // Offset 18h size 4
77+
UINT32 RpPioException; // Offset 1Ch size 4
78+
UINT32 RpPioHdrLog[4]; // Offset 20h size 16 header log DW 1-4
79+
UINT32 RpPioImpSpecLog; // Offset 30h size 4
80+
UINT32 RpPioHdrLogExt[10]; // Offset 34h size 40 header log DW 5-14
81+
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DPC;
82+
83+
//
84+
// L1 PM Substates Extended Capability.
85+
//
1886
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
1987
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1
2088

@@ -67,31 +135,32 @@ typedef struct {
67135
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
68136
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
69137

70-
/// Process Address Space ID Extended Capability Structure
71-
///
72-
/// Based on section 7.29 of PCI Express Base Specification 3.1
73-
///@{
138+
//
139+
// Process Address Space ID (PASID) Extended Capability Structure.
140+
//
74141
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B
75142
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1
76143

77144
typedef union {
78145
struct {
79-
UINT16 PasidSupport : 1;
80-
UINT16 ExecutePermissionSupport : 1;
81-
UINT16 PrivilegedModeSupport : 1;
82-
UINT16 Reserved1 : 5;
83-
UINT16 MaxPasidWidth : 5;
84-
UINT16 Reserved2 : 3;
146+
UINT16 Reserved0 : 1; // [0]
147+
UINT16 ExecutePermissionSupport : 1; // [1]
148+
UINT16 PrivilegedModeSupport : 1; // [2]
149+
UINT16 TranslatedReqWithPasidSupport : 1; // [3]
150+
UINT16 Reserved1 : 4; // [7:4]
151+
UINT16 MaxPasidWidth : 5; // [12:8]
152+
UINT16 Reserved2 : 3; // [15:13]
85153
} Bits;
86154
UINT16 Uint16;
87155
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY;
88156

89157
typedef union {
90158
struct {
91-
UINT16 PasidEnable : 1;
92-
UINT16 ExecutePermissionEnable : 1;
93-
UINT16 PrivilegedModeEnable : 1;
94-
UINT16 Reserved : 13;
159+
UINT16 PasidEnable : 1; // [0]
160+
UINT16 ExecutePermissionEnable : 1; // [1]
161+
UINT16 PrivilegedModeEnable : 1; // [2]
162+
UINT16 TranslatedReqWithPasidEnable : 1; // [3]
163+
UINT16 Reserved : 12;
95164
} Bits;
96165
UINT16 Uint16;
97166
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL;
@@ -101,7 +170,6 @@ typedef struct {
101170
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability;
102171
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control;
103172
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID;
104-
///@}
105173

106174
#pragma pack()
107175

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