From f4ec13e7c9dbe744406540936adf837c490d3e01 Mon Sep 17 00:00:00 2001 From: Jacek Kolakowski Date: Thu, 13 Nov 2025 11:54:43 +0100 Subject: [PATCH 1/3] UefiPayloadPkg: Remove PcdMrIovSupport - deprecated in PCIe 6.0 MR-IOV was actually not used in MdeModulePkg and it has been deprecated in PCIe 6.0 specification, so remove it. Signed-off-by: Jacek Kolakowski --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc index fa18876345ea..aad751c7f8dc 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -783,7 +783,6 @@ [PcdsDynamicExDefault] gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1 From bfcf60e4761892fc982225c1be6e1b4b853f7929 Mon Sep 17 00:00:00 2001 From: Jacek Kolakowski Date: Thu, 13 Nov 2025 12:14:02 +0100 Subject: [PATCH 2/3] MdeModulePkg: Remove PcdMrIovSupport - deprecated in PCIe 6.0 MR-IOV was actually not used in MdeModulePkg and it has been deprecated in PCIe 6.0 specification, so remove it. Signed-off-by: Jacek Kolakowski --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 2 -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 - .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 12 ------------ MdeModulePkg/MdeModulePkg.dec | 6 ------ MdeModulePkg/MdeModulePkg.uni | 6 ------ 5 files changed, 27 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index ca5c06204dec..510779429852 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -51,7 +51,6 @@ typedef struct _PCI_BAR PCI_BAR; #define EFI_PCI_IOV_POLICY_ARI 0x0001 #define EFI_PCI_IOV_POLICY_SRIOV 0x0002 -#define EFI_PCI_IOV_POLICY_MRIOV 0x0004 typedef enum { PciBarTypeUnknown = 0, @@ -269,7 +268,6 @@ struct _PCI_IO_DEVICE { UINT8 PciExpressCapabilityOffset; UINT32 AriCapabilityOffset; UINT32 SrIovCapabilityOffset; - UINT32 MrIovCapabilityOffset; PCI_BAR VfPciBar[PCI_MAX_BAR]; UINT32 SystemPageSize; UINT16 InitialVFs; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 6a0dc08cb7f3..eea52ee1eb6f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -94,7 +94,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUMES diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 5c4b215f7ac7..278a0eb9c430 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -2460,18 +2460,6 @@ CreatePciIoDevice ( } } - if (PcdGetBool (PcdMrIovSupport)) { - Status = LocatePciExpressCapabilityRegBlock ( - PciIoDevice, - EFI_PCIE_CAPABILITY_ID_MRIOV, - &PciIoDevice->MrIovCapabilityOffset, - NULL - ); - if (!EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset)); - } - } - PciIoDevice->ResizableBarOffset = 0; if (PcdGetBool (PcdPcieResizableBarSupport)) { Status = LocatePciExpressCapabilityRegBlock ( diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 979188e52943..cc8417999467 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2050,12 +2050,6 @@ # @Prompt Enable ARI support. gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE|BOOLEAN|0x10000045 - ## Indicates if the Multi Root I/O virtualization is supported.

- # TRUE - Multi Root I/O virtualization is supported.
- # FALSE - Multi Root I/O virtualization is not supported.
- # @Prompt Enable MRIOV support. - gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE|BOOLEAN|0x10000046 - ## Single root I/O virtualization virtual function memory BAR alignment.

# BITN set indicates 2 of n+12 power
# BIT0 set indicates 4KB alignment
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni index cce8426bb9d2..f5c442fc7967 100644 --- a/MdeModulePkg/MdeModulePkg.uni +++ b/MdeModulePkg/MdeModulePkg.uni @@ -560,12 +560,6 @@ "TRUE - Alternative Routing-ID is supported.
\n" "FALSE - Alternative Routing-ID is not supported.
" -#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdMrIovSupport_PROMPT #language en-US "Enable MRIOV support" - -#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdMrIovSupport_HELP #language en-US "Indicates if the Multi Root I/O virtualization is supported.

\n" - "TRUE - Multi Root I/O virtualization is supported.
\n" - "FALSE - Multi Root I/O virtualization is not supported.
" - #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSrIovSystemPageSize_PROMPT #language en-US "SRIOV system page size" #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSrIovSystemPageSize_HELP #language en-US "Single root I/O virtualization virtual function memory BAR alignment.

\n" From 87816cd95fbddedfaef9f43b8e13582b735d1f9c Mon Sep 17 00:00:00 2001 From: Jacek Kolakowski Date: Thu, 13 Nov 2025 12:21:04 +0100 Subject: [PATCH 3/3] MdePkg: Add PCIe capability structures for DPC and DLF Add definitions for Downstream Port Containment (DPC) Extended Capability. Add definitions for Data Link Feature (DLF). Update existing definitions for Process Address Space ID (PASID). Update existing definitions for Precision Time Measurement (PTM). Mark some duplicate symbols 'obsolete' to remove it in future. Signed-off-by: Jacek Kolakowski --- MdePkg/Include/IndustryStandard/Pci30.h | 8 +- .../Include/IndustryStandard/PciExpress21.h | 83 +++++++++------- .../Include/IndustryStandard/PciExpress31.h | 98 ++++++++++++++++--- .../Include/IndustryStandard/PciExpress40.h | 78 ++++++++++----- 4 files changed, 190 insertions(+), 77 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h index 108ab6165ae4..eb4e0e3715c3 100644 --- a/MdePkg/Include/IndustryStandard/Pci30.h +++ b/MdePkg/Include/IndustryStandard/Pci30.h @@ -39,9 +39,11 @@ **/ #define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA) -/// -/// PCI Capability List IDs and records -/// +// +// Symbol EFI_PCI_CAPABILITY_ID_PCIEXP is obsolete, use PCI_EXPRESS_CAPABILITY_ID. +// PCI_EXPRESS_CAPABILITY_ID is defined beside the capability registers structure +// in PciExpress21.h. This ID is not EFI nor PCI symbol, but PCI Express. +// #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10 #pragma pack(1) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index 7d0fa95148f6..50436bfdd575 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -30,9 +30,17 @@ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) #pragma pack(1) -/// -/// PCI Express Capability Structure -/// + +// +// PCI Express Capability Structure version 2. +// Mandatory for PCI Express devices. If not present it is not PCI Express device, thus no extended config space. +// Version 1 ends at PCI_CAPABILITY_PCIEXP::RootStatus register. +// Version 2 extends version 1 up to PCI_CAPABILITY_PCIEXP::SlotStatus2 register. +// +#define PCI_EXPRESS_CAPABILITY_ID 0x0010 +#define PCI_EXPRESS_CAPABILITY_VER1 0x1 +#define PCI_EXPRESS_CAPABILITY_VER2 0x2 + typedef union { struct { UINT16 Version : 4; @@ -397,29 +405,29 @@ typedef union { } PCI_REG_PCIE_SLOT_CAPABILITY2; typedef struct { - EFI_PCI_CAPABILITY_HDR Hdr; - PCI_REG_PCIE_CAPABILITY Capability; - PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; - PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; - PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; - PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; - PCI_REG_PCIE_LINK_CONTROL LinkControl; - PCI_REG_PCIE_LINK_STATUS LinkStatus; - PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; - PCI_REG_PCIE_SLOT_CONTROL SlotControl; - PCI_REG_PCIE_SLOT_STATUS SlotStatus; - PCI_REG_PCIE_ROOT_CONTROL RootControl; - PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; - PCI_REG_PCIE_ROOT_STATUS RootStatus; - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; - PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; - UINT16 DeviceStatus2; - PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; - PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; - PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; - PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2; - UINT16 SlotControl2; - UINT16 SlotStatus2; + EFI_PCI_CAPABILITY_HDR Hdr; // Offset 00 size 2 + PCI_REG_PCIE_CAPABILITY Capability; // Offset 02 size 2 + PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; // Offset 04 size 4 + PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; // Offset 08 size 2 + PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; // Offset 0A size 2 + PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; // Offset 0C size 4 + PCI_REG_PCIE_LINK_CONTROL LinkControl; // Offset 10 size 2 + PCI_REG_PCIE_LINK_STATUS LinkStatus; // Offset 12 size 2 + PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; // Offset 14 size 4 + PCI_REG_PCIE_SLOT_CONTROL SlotControl; // Offset 18 size 2 + PCI_REG_PCIE_SLOT_STATUS SlotStatus; // Offset 1A size 2 + PCI_REG_PCIE_ROOT_CONTROL RootControl; // Offset 1C size 2 + PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; // Offset 1E size 2 + PCI_REG_PCIE_ROOT_STATUS RootStatus; // Offset 20 size 4 - Ver1 ends here + PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; // Offset 24 size 4 + PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; // Offset 28 size 2 + UINT16 DeviceStatus2; // Offset 2A size 2 + PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; // Offset 2C size 4 + PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; // Offset 30 size 2 + PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; // Offset 32 size 2 + PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2; // Offset 34 size 4 + UINT16 SlotControl2; // Offset 38 size 2 + UINT16 SlotStatus2; // Offset 3A size 2 } PCI_CAPABILITY_PCIEXP; #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100 @@ -430,13 +438,18 @@ typedef struct { #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20 // -// for SR-IOV +// Definitions EFI_PCIE_CAPABILITY_ID_ARI, EFI_PCIE_CAPABILITY_ID_ATS, EFI_PCIE_CAPABILITY_ID_SRIOV, +// are obsolete, will be removed in future. Instead use PCI Express definitions +// PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID, PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID, +// PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID. // -#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E -#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F -#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10 -#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11 +#define EFI_PCIE_CAPABILITY_ID_ARI PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID +#define EFI_PCIE_CAPABILITY_ID_ATS PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID +#define EFI_PCIE_CAPABILITY_ID_SRIOV PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID +// +// Single Root IO Virtualization (SR-IOV) Extended Capability Structure. +// #define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID 0x0010 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_VER1 0x1 @@ -740,10 +753,9 @@ typedef struct { #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16) -/// Address Translation Services Extended Capability Structure -/// -/// Based on section 5.1 of PCI Express Address Translation Services Specification 1.1 -///@{ +// +// Address Translation Services (ATS) Extended Capability Structure. +// #define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID 0x000F #define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_VER1 0x1 @@ -771,7 +783,6 @@ typedef struct { PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY Capability; PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL Control; } PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS; -///@} #pragma pack() diff --git a/MdePkg/Include/IndustryStandard/PciExpress31.h b/MdePkg/Include/IndustryStandard/PciExpress31.h index 7c291fbe2ae2..8efc6ffe17a8 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress31.h +++ b/MdePkg/Include/IndustryStandard/PciExpress31.h @@ -15,6 +15,74 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack(1) +// +// Downstream Port Containment (DPC) Extended Capability. +// +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DPC_ID 0x001D + +typedef union { + struct { + UINT16 DpcInterruptMsgNo : 5; // [4:0] + UINT16 RpExtensionsForDpc : 1; // [5] + UINT16 PoisonedTlpEgressBlockingSupp : 1; // [6] + UINT16 DpcSoftwareTriggerSupp : 1; // [7] + UINT16 RpPioLogSize : 4; // [11:8] Bits [3:0] of log size + UINT16 DlActiveErrCorSignalingSupp : 1; // [12] + UINT16 RpPioLogSizeExt : 1; // [13] Bit [4] of log size + UINT16 Reserved : 2; // [15:14] + } Bits; + UINT32 Uint16; +} PCI_EXPRESS_REG_DPC_CAPABILITY; + +typedef union { + struct { + UINT16 DpcTriggerEn : 2; // [1:0] + UINT16 DpcCompletionCtl : 1; // [2] + UINT16 DpcInterruptEn : 1; // [3] + UINT16 DpcErrCorEn : 1; // [4] + UINT16 PoisonedTlpEgressBlockingEn : 1; // [5] + UINT16 DpcSoftwareTrigger : 1; // [6] + UINT16 DlActiveErrCorEn : 1; // [7] + UINT16 DpcSigSfwEn : 1; // [8] + UINT16 Reserved : 7; // [15:9] + } Bits; + UINT16 Uint16; +} PCI_EXPRESS_REG_DPC_CONTROL; + +typedef union { + struct { + UINT16 DpcTriggerStatus : 1; // [0] + UINT16 DpcTriggerReason : 2; // [2:1] + UINT16 DpcInterruptStatus : 1; // [3] + UINT16 DpcRpBusy : 1; // [4] + UINT16 DpcTriggerReasonExtension : 2; // [6:5] + UINT16 Reserved0 : 1; // [7] + UINT16 RpPioFirstErrorPointer : 5; // [12:8] + UINT16 DpcSigSfwStatus : 1; // [13] + UINT16 Reserved1 : 2; // [15:14] + } Bits; + UINT16 Uint16; +} PCI_EXPRESS_REG_DPC_STATUS; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_DPC_CAPABILITY Capability; // Offset 04h size 2 + PCI_EXPRESS_REG_DPC_CONTROL Control; // Offset 06h size 2 + PCI_EXPRESS_REG_DPC_STATUS Status; // Offset 08h size 2 + UINT16 ErrSourceId; // Offset 0Ah size 2 + UINT32 RpPioStatus; // Offset 0Ch size 4 + UINT32 RpPioMask; // Offset 10h size 4 + UINT32 RpPioSeverity; // Offset 14h size 4 + UINT32 RpPioSysErr; // Offset 18h size 4 + UINT32 RpPioException; // Offset 1Ch size 4 + UINT32 RpPioHdrLog[4]; // Offset 20h size 16 header log DW 1-4 + UINT32 RpPioImpSpecLog; // Offset 30h size 4 + UINT32 RpPioHdrLogExt[10]; // Offset 34h size 40 header log DW 5-14 +} PCI_EXPRESS_EXTENDED_CAPABILITIES_DPC; + +// +// L1 PM Substates Extended Capability. +// #define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E #define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1 @@ -67,31 +135,32 @@ typedef struct { PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2; } PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES; -/// Process Address Space ID Extended Capability Structure -/// -/// Based on section 7.29 of PCI Express Base Specification 3.1 -///@{ +// +// Process Address Space ID (PASID) Extended Capability Structure. +// #define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B #define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1 typedef union { struct { - UINT16 PasidSupport : 1; - UINT16 ExecutePermissionSupport : 1; - UINT16 PrivilegedModeSupport : 1; - UINT16 Reserved1 : 5; - UINT16 MaxPasidWidth : 5; - UINT16 Reserved2 : 3; + UINT16 Reserved0 : 1; // [0] + UINT16 ExecutePermissionSupport : 1; // [1] + UINT16 PrivilegedModeSupport : 1; // [2] + UINT16 TranslatedReqWithPasidSupport : 1; // [3] + UINT16 Reserved1 : 4; // [7:4] + UINT16 MaxPasidWidth : 5; // [12:8] + UINT16 Reserved2 : 3; // [15:13] } Bits; UINT16 Uint16; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY; typedef union { struct { - UINT16 PasidEnable : 1; - UINT16 ExecutePermissionEnable : 1; - UINT16 PrivilegedModeEnable : 1; - UINT16 Reserved : 13; + UINT16 PasidEnable : 1; // [0] + UINT16 ExecutePermissionEnable : 1; // [1] + UINT16 PrivilegedModeEnable : 1; // [2] + UINT16 TranslatedReqWithPasidEnable : 1; // [3] + UINT16 Reserved : 12; } Bits; UINT16 Uint16; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL; @@ -101,7 +170,6 @@ typedef struct { PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability; PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID; -///@} #pragma pack() diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h index d28f5e71d03c..79d9568bd2ef 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress40.h +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -16,47 +16,79 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack(1) -/// Precision Time Management Extended Capability definitions. -/// -/// Based on section 7.9.16 of PCI Express Base Specification 4.0. -///@{ +// +// Precision Time Measurement (PTM) Extended Capability. +// #define PCI_EXPRESS_EXTENDED_CAPABILITY_PTM_ID 0x001F #define PCI_EXPRESS_EXTENDED_CAPABILITY_PTM_VER1 0x1 -#define PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY_OFFSET 0x04 -#define PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL_OFFSET 0x08 - typedef union { struct { - UINT32 PTMRequesterCapable : 1; - UINT32 PTMResponderCapable : 1; - UINT32 PTMRootCapable : 1; - UINT32 ePTMCapable : 1; - UINT32 PTMPropagationDelayAdaptationCapable : 1; - UINT32 Reserved : 3; - UINT32 LocalClockGranularity : 8; - UINT32 Reserved2 : 16; + UINT32 PtmRequesterCapable : 1; // [0] + UINT32 PtmResponderCapable : 1; // [1] + UINT32 PtmRootCapable : 1; // [2] + UINT32 EPtmCapable : 1; // [3] + UINT32 PtmPropatagionDelayAdaptCapable : 1; // [4] + UINT32 Reserved0 : 3; // [7:5] + UINT32 LocalClockGranularity : 8; // [15:8] + UINT32 Reserved1 : 16; // [31:16] } Bits; UINT32 Uint32; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY; typedef union { struct { - UINT32 PTMEnable : 1; - UINT32 RootSelect : 1; - UINT32 Reserved : 6; - UINT32 EffectiveGranularity : 8; - UINT32 Reserved2 : 16; + UINT32 PtmEnable : 1; // [0] + UINT32 RootSelect : 1; // [1] + UINT32 Reserved0 : 6; // [7:2] + UINT32 EffectiveGranularity : 8; // [15:8] + UINT32 Reserved1 : 16; // [31:16] } Bits; UINT32 Uint32; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL; typedef struct { PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; - PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY Capability; - PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL Control; + PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CAPABILITY Capability; // Offset 04h size 4 + PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM_CONTROL Control; // Offset 08h size 4 } PCI_EXPRESS_EXTENDED_CAPABILITIES_PTM; -///@} + +// +// Data Link Feature (DLF) Extended Capability. +// +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DLF_ID 0x0025 + +typedef union { + struct { + UINT32 LocalScaledFlowControlSupported : 1; // [0] + UINT32 LocalImmediateReadiness : 1; // [1] + UINT32 LocalExtendedVcCount : 3; // [4:2] + UINT32 LocalL0pExitLatency : 3; // [7:5] + UINT32 Reserved0 : 15; // [22:8] + UINT32 Reserved1 : 8; // [30:23] + UINT32 DataLinkFeatureExchangeEnable : 1; // [31] + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_DLF_CAPABILITY; + +typedef union { + struct { + UINT32 RemoteScaledFlowControlSupported : 1; // [0] + UINT32 RemoteImmediateReadiness : 1; // [1] + UINT32 ExtendedVcCound : 3; // [4:2] + UINT32 RemoteL0pExitLatency : 3; // [7:5] + UINT32 Reserved0 : 15; // [22:8] + UINT32 Reserved1 : 8; // [30:23] + UINT32 DataLinkFeatureStatusValid : 1; // [31] + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_DLF_STATUS; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_DLF_CAPABILITY Capability; + PCI_EXPRESS_REG_DLF_STATUS Status; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_DLF; /// The Physical Layer PCI Express Extended Capability definitions. ///