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Made FPGA inside view render compact_input gates correctly (#3547)
1 parent 84c01cd commit b72afcc

1 file changed

Lines changed: 17 additions & 2 deletions

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lua/entities/gmod_wire_fpga/init.lua

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,21 @@ end
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function ENT:SynthesizeViewData(data)
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if not data.Nodes then return end
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function getInputAmountForNode(node)
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local gate = getGate(node)
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local amountOfInputs = 0
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if gate.compact_inputs then
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inputLimit = gate.compact_inputs
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for inputIdx, _ in pairs(node.connections) do
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inputLimit = math.max(inputLimit, inputIdx + 1)
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end
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amountOfInputs = math.min(#gate.inputs, inputLimit)
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else
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amountOfInputs = #gate.inputs
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end
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return amountOfInputs
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end
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local viewData = {}
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viewData.Nodes = {}
@@ -247,9 +262,9 @@ function ENT:SynthesizeViewData(data)
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local ports
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if gate.outputs then
250-
ports = math.max(#gate.inputs, #gate.outputs)
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ports = math.max(getInputAmountForNode(node), #gate.outputs)
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else
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ports = #gate.inputs
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ports = getInputAmountForNode(node)
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end
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table.insert(viewData.Nodes, {

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