Add minimal Verilog frontend

[rollrat]

Summary

• add a minimal Verilog frontend for assign-based combinational modules
• lower parsed Verilog into LogicGraph, including simple bit-select flattening and named module instance inlining
• wire .v CLI loading and tiny-circuit NBT export, with main flow simplified using early returns

Test Plan

• cargo test --release
• cargo test --release verilog::
• cargo run --release --bin redstone-compiler -- test/half-adder.v
• cargo run --release --bin redstone-compiler -- test/half-adder.v test/half-adder-generated-from-verilog.nbt