parser: add asm parsing

Cargo.toml

@@ -6,3 +6,4 @@ edition = "2021"
 [dependencies]
 strum = "0.21.0"
 strum_macros = "0.21.1"
+regex = "1.10.4"

src/instruction.rs

@@ -1,6 +1,5 @@
 use std::convert::Into;
-use std::default;
-use std::fmt::{format, write, Display};
+use std::fmt::Display;
 
 /// This file defines all the supported ARM and RISC-V instructions we support.
 /// We use `strum` to assist in serializing asm files to our [`Instruction`] enum.
@@ -133,7 +132,7 @@ pub enum RiscVInstruction {
     Slli {
         dest: RiscVRegister,
         src: RiscVRegister,
-        imm: i32
+        imm: i32,
     },
     /// Loads a value from memory into register rd for RV64I.
     ///
@@ -373,7 +372,7 @@ pub enum ArmInstruction {
     Lsl {
         dest: ArmRegister,
         src: ArmRegister,
-        imm: i32
+        imm: i32,
     },
     /// Str [r2 + offset] = r1
     #[strum(serialize = "str")]
@@ -426,7 +425,7 @@ impl Default for ArmInstruction {
     }
 }
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq, Clone)]
 pub enum RiscVVal {
     RiscVRegister(RiscVRegister),
     Immediate(i32),
@@ -449,7 +448,7 @@ impl Default for RiscVVal {
 
 /// RISC-V Registers
 /// https://msyksphinz-self.github.io/riscv-isadoc/html/regs.html
-#[derive(Debug, EnumString, Default)]
+#[derive(Debug, EnumString, Default, PartialEq, Eq, Clone)]
 pub enum RiscVRegister {
     #[default]
     #[strum(serialize = "x0")]

src/lib.rs

@@ -1,3 +1,4 @@
 pub mod instruction;
+pub mod parser;
 pub mod translate;
 pub mod utils;

src/main.rs

@@ -1,9 +1,7 @@
 use std::fs;
-use std::str::FromStr;
 pub mod instruction;
 pub mod translate;
 pub mod utils;
-use instruction::RiscVInstruction;
 use translate::binary_translate;
 
 // Samir: I am using main for testing, but it not needed since you can run