Implement RISCV Translation #5
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Corrected the translation between registers for our 64 bit architectures.
…inary-room into register-enum-translation
Collaborator
|
lgtm |
Owner
Author
|
Tested and works @trdavidt Please review, approve, and merge when you have a chance. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This pull request includes significant changes to the project, focusing on adding new translation functionalities, modifying existing modules, and updating test files. The most important changes include the addition of translation logic from RISC-V to ARM instructions, restructuring of the main module, and updates to the testing framework.
Translation Functionality:
src/translate.rs: Introduced comprehensive translation logic from RISC-V to ARM instructions, including detailed mappings for various instruction types and registers.Module Restructuring:
src/main.rs: Refactored the main module to import new submodules (instruction,translate,utils) and removed the old parsing and translation functions.src/lib.rs: Added new submodules to the library, enabling modular access to instruction parsing, translation, and utility functions.Testing and Examples:
tests/binaries/add.c: Reintroduced the example C program for testing purposes, including commented sections for RISC-V and ARM assembly comparisons.test_binary_translate_add.S: Added a new assembly file to test the binary translation functionality.