organize tests

src/utils.rs

@@ -27,5 +27,6 @@ pub fn translate_to_file(instrs: Vec<RiscVInstruction>, path: String) {
         contents.push_str(&x);
         contents.push_str("\n");
     }
-    fs::write(path, contents).expect("Unable to write file");
+    fs::write(&path, contents).expect("Unable to write file");
+    println!("Saved ARM assembly to {}", path);
 }

tests/add/test_add.rs

@@ -0,0 +1,125 @@
+#[cfg(test)]
+mod tests {
+    use binary_room::instruction::*;
+    use binary_room::translate::*;
+    use binary_room::utils;
+    use binary_room::utils::translate_to_file;
+    use binary_room::utils::START;
+
+    #[test]
+    fn test_binary_translate() {
+        let riscv_asm: Vec<RiscVInstruction> = vec![
+            RiscVInstruction::Verbatim { text: START.to_string() },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::SP,
+                src: RiscVRegister::SP,
+                imm: -32,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Double,
+                src: RiscVRegister::RA,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 24,
+                },
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Double,
+                src: RiscVRegister::S0FP,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 16,
+                },
+            },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::S0FP,
+                src: RiscVRegister::SP,
+                imm: 32,
+            },
+            RiscVInstruction::Li {
+                dest: RiscVRegister::A5,
+                imm: 3,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Word,
+                src: RiscVRegister::A5,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -20,
+                },
+            },
+            RiscVInstruction::Li {
+                dest: RiscVRegister::A5,
+                imm: 4,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Word,
+                src: RiscVRegister::A5,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -24,
+                },
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -20,
+                },
+            },
+            RiscVInstruction::Mv {
+                dest: RiscVRegister::A4,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -24,
+                },
+            },
+            RiscVInstruction::Add {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                arg1: RiscVRegister::A4,
+                arg2: RiscVRegister::A5,
+            },
+            RiscVInstruction::SextW {
+                dest: RiscVRegister::A5,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::Mv {
+                dest: RiscVRegister::A0,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Double,
+                dest: RiscVRegister::RA,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 24,
+                },
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Double,
+                dest: RiscVRegister::S0FP,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 16,
+                },
+            },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::SP,
+                src: RiscVRegister::SP,
+                imm: 32,
+            },
+            RiscVInstruction::Jr {
+                target: RiscVRegister::RA,
+            },
+        ];
+
+        translate_to_file(riscv_asm, "./tests/add/add.arm.s".to_string());
+    }
+}

tests/echo/echo.arm.s

@@ -0,0 +1,29 @@
+
+.text
+
+.global _start
+.global _main
+
+.balign 4
+_start:
+bl main
+mov x8, #93
+svc #0
+
+.balign 4
+_main:
+main:
+
+sub sp, sp, 32
+mov x8, 63
+mov x2, 32
+add x1, sp, 0
+mov x0, 0
+svc 0
+mov x8, 64
+mov x2, 14
+add x1, sp, 0
+mov x0, 1
+svc 0
+mov x8, 93
+svc 0

tests/test_echo.rs → tests/echo/test_echo.rs

@@ -68,6 +68,6 @@ mod tests {
             RiscVInstruction::ECall,
         ];
 
-        translate_to_file(riscv_asm, "test_binary_translate_echo.S".to_string());
+        translate_to_file(riscv_asm, "./tests/echo/echo.arm.s".to_string());
     }
 }

tests/print/print.arm.s

@@ -0,0 +1,28 @@
+
+.buf:
+    .string "hello world\n"
+
+
+.text
+
+.global _start
+.global _main
+
+.balign 4
+_start:
+bl main
+mov x8, #93
+svc #0
+
+.balign 4
+_main:
+main:
+
+mov x8, 64
+mov x2, 14
+adrp x0, .buf
+add x1, x0, :lo12:.buf
+mov x0, 1
+svc 0
+mov x8, 93
+svc 0

tests/test_print.rs → tests/print/test_print.rs

@@ -58,6 +58,6 @@ mod tests {
             RiscVInstruction::ECall,
         ];
 
-        translate_to_file(riscv_asm, "test_binary_translate_print.S".to_string());
+        translate_to_file(riscv_asm, "./tests/print/print.arm.s".to_string());
     }
 }

tests/tests.rs

@@ -0,0 +1,8 @@
+#[path = "add/test_add.rs"]
+mod add;
+
+#[path = "echo/test_echo.rs"]
+mod echo;
+
+#[path = "print/test_print.rs"]
+mod print;