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ExaNIC_X25/fpga_10g/common Expand file tree Collapse file tree 16 files changed +64
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lines changed Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
Original file line number Diff line number Diff line change @@ -59,6 +59,9 @@ all: fpga
5959
6060fpga : $(FPGA_TOP ) .bit
6161
62+ vivado : $(FPGA_TOP ) .xpr
63+ vivado $(FPGA_TOP ) .xpr
64+
6265tmpclean :
6366 -rm -rf * .log * .jou * .cache * .hbs * .hw * .ip_user_files * .runs * .xpr * .html * .xml * .sim * .srcs * .str .Xil defines.v
6467 -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
@@ -74,7 +77,7 @@ distclean: clean
7477# ##################################################################
7578
7679# Vivado project file
77- % .xpr : Makefile $(XCI_FILES_REL )
80+ % .xpr : Makefile $(XCI_FILES_REL ) $( IP_TCL_FILES_REL )
7881 rm -rf defines.v
7982 touch defines.v
8083 for x in $( DEFS) ; do echo ' `define' $$ x >> defines.v; done
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