Clean up clock connections

alexforencich · alexforencich · commit fd908dd2aa69 · 2020-08-06T17:15:38.000-07:00
diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
@@ -96,9 +96,9 @@ module fpga (
 // Clock and reset
 
 wire clk_300mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -96,9 +96,9 @@ module fpga (
 // Clock and reset
 
 wire clk_300mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/ATLYS/fpga/rtl/fpga.v b/example/ATLYS/fpga/rtl/fpga.v
@@ -72,10 +72,9 @@ module fpga (
 // Clock and reset
 
 wire clk_ibufg;
-wire clk_bufg;
-wire clk_dcm_out;
 
 // Internal 125 MHz clock
+wire clk_dcm_out;
 wire clk_int;
 wire rst_int;
 
diff --git a/example/AU280/fpga_10g/rtl/fpga.v b/example/AU280/fpga_10g/rtl/fpga.v
@@ -94,9 +94,8 @@ module fpga (
 
 wire clk_161mhz_ref_int;
 
-wire clk_125mhz_mmcm_out;
-
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/AU50/fpga_10g/rtl/fpga.v b/example/AU50/fpga_10g/rtl/fpga.v
@@ -67,9 +67,8 @@ module fpga (
 
 wire clk_161mhz_ref_int;
 
-wire clk_125mhz_mmcm_out;
-
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/Arty/fpga/rtl/fpga.v b/example/Arty/fpga/rtl/fpga.v
@@ -84,10 +84,9 @@ module fpga (
 // Clock and reset
 
 wire clk_ibufg;
-wire clk_bufg;
-wire clk_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_mmcm_out;
 wire clk_int;
 wire rst_int;
 
diff --git a/example/ExaNIC_X10/fpga/rtl/fpga.v b/example/ExaNIC_X10/fpga/rtl/fpga.v
@@ -69,9 +69,9 @@ module fpga (
 // Clock and reset
 
 wire clk_100mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/ExaNIC_X25/fpga_10g/rtl/fpga.v b/example/ExaNIC_X25/fpga_10g/rtl/fpga.v
@@ -64,9 +64,8 @@ module fpga (
 
 wire clk_161mhz_int;
 
-wire clk_125mhz_mmcm_out;
-
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/KC705/fpga_gmii/rtl/fpga.v b/example/KC705/fpga_gmii/rtl/fpga.v
@@ -76,12 +76,11 @@ module fpga (
 // Clock and reset
 
 wire clk_200mhz_ibufg;
-wire clk_200mhz_bufg;
-wire clk_200mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_mmcm_out;
 wire clk_int;
-wire rst_int;   
+wire rst_int;
 
 wire mmcm_rst = reset;
 wire mmcm_locked;
diff --git a/example/ML605/fpga_gmii/rtl/fpga.v b/example/ML605/fpga_gmii/rtl/fpga.v
@@ -77,10 +77,9 @@ module fpga (
 // Clock and reset
 
 wire sys_clk_ibufg;
-wire sys_clk_bufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/ML605/fpga_rgmii/rtl/fpga.v b/example/ML605/fpga_rgmii/rtl/fpga.v
@@ -74,12 +74,11 @@ module fpga (
 // Clock and reset
 
 wire sys_clk_ibufg;
-wire sys_clk_bufg;
-wire clk_125mhz_mmcm_out;
-wire clk90_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
+wire clk90_125mhz_mmcm_out;
 wire clk90_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/ML605/fpga_sgmii/rtl/fpga.v b/example/ML605/fpga_sgmii/rtl/fpga.v
@@ -74,10 +74,9 @@ module fpga (
 // Clock and reset
 
 wire sys_clk_ibufg;
-wire sys_clk_bufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga.v b/example/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -100,9 +100,9 @@ module fpga (
 // Clock and reset
 
 wire clk_200mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/NexysVideo/fpga/rtl/fpga.v b/example/NexysVideo/fpga/rtl/fpga.v
@@ -71,10 +71,9 @@ module fpga (
 // Clock and reset
 
 wire clk_ibufg;
-wire clk_bufg;
-wire clk_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_mmcm_out;
 wire clk_int;
 wire rst_int;   
 
diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v
@@ -110,9 +110,9 @@ module fpga (
 // Clock and reset
 
 wire clk_125mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/VCU108/fpga_1g/rtl/fpga.v b/example/VCU108/fpga_1g/rtl/fpga.v
@@ -73,9 +73,9 @@ module fpga (
 // Clock and reset
 
 wire clk_125mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/VCU118/fpga_10g/rtl/fpga.v b/example/VCU118/fpga_10g/rtl/fpga.v
@@ -140,9 +140,9 @@ module fpga (
 // Clock and reset
 
 wire clk_125mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/VCU118/fpga_1g/rtl/fpga.v b/example/VCU118/fpga_1g/rtl/fpga.v
@@ -75,9 +75,9 @@ module fpga (
 // Clock and reset
 
 wire clk_125mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/VCU118/fpga_25g/rtl/fpga.v b/example/VCU118/fpga_25g/rtl/fpga.v
@@ -140,9 +140,9 @@ module fpga (
 // Clock and reset
 
 wire clk_125mhz_ibufg;
-wire clk_125mhz_mmcm_out;
 
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
diff --git a/example/VCU1525/fpga_10g/rtl/fpga.v b/example/VCU1525/fpga_10g/rtl/fpga.v
@@ -119,9 +119,8 @@ wire cfgmclk_int;
 
 wire clk_161mhz_ref_int;
 
-wire clk_125mhz_mmcm_out;
-
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
