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Added VMK180 example design
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‎example/VMK180/fpga/README.md‎

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# Verilog PCIe VMK180 Example Design
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## Introduction
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This example design targets the Xilinx VMK180 FPGA board.
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The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design.
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* FPGA: xcvm1802-vsva2197-2MP-e-S
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## How to build
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Run `make` to build. Ensure that the Xilinx Vivado components are in PATH.
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Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run `make program` to program the VCU180 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output.

‎example/VMK180/fpga/common/vivado.mk‎

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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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# Copyright (c) 2025 Jonathan Drolet
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).pdi
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vivado: $(FPGA_TOP).xpr
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vivado $(FPGA_TOP).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str *.bif *.rcdo *.rnpi gen_files static_files .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_pdi.tcl
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clean:: tmpclean
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-rm -rf *.pdi program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL)
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echo "open_project -quiet $(FPGA_TOP).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# pdi file
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%.pdi: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_pdi.tcl
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echo "open_run impl_1" >> generate_pdi.tcl
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echo "write_device_image -force $*.pdi" >> generate_pdi.tcl
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vivado -nojournal -nolog -mode batch -source generate_pdi.tcl
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mkdir -p rev
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EXT=pdi; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";

‎example/VMK180/fpga/driver‎

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../../common/driver/example/

‎example/VMK180/fpga/fpga.xdc‎

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# XDC constraints for the Xilinx VMK180 board
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# part: xcvm1802-vsva2197-2MP-e-S
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# LEDs
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set_property -dict {LOC H34 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC J33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC K36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC L35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# DIP switches
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set_property -dict {LOC J35 IOSTANDARD LVCMOS18} [get_ports {sw[0]}]
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set_property -dict {LOC J34 IOSTANDARD LVCMOS18} [get_ports {sw[1]}]
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set_property -dict {LOC H37 IOSTANDARD LVCMOS18} [get_ports {sw[2]}]
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set_property -dict {LOC H36 IOSTANDARD LVCMOS18} [get_ports {sw[3]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# PCIe clock
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set_property -dict {LOC W39 } [get_ports pcie_clk0_p] ;# GTY_REFCLKP0_103
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set_property -dict {LOC W40 } [get_ports pcie_clk0_n] ;# GTY_REFCLKN0_103
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create_clock -period 10.000 -name pcie_clk [get_ports pcie_clk0_p]
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# PCIe Interface
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set_property -dict {LOC AB46 } [get_ports {pcie_rx_p[0]}] ;# GTY_RXP0_103
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set_property -dict {LOC AB47 } [get_ports {pcie_rx_n[0]}] ;# GTY_RXN0_103
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set_property -dict {LOC AB41 } [get_ports {pcie_tx_p[0]}] ;# GTY_TXP0_103
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set_property -dict {LOC AB42 } [get_ports {pcie_tx_n[0]}] ;# GTY_TXN0_103
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set_property -dict {LOC AA44 } [get_ports {pcie_rx_p[1]}] ;# GTY_RXP2_103
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set_property -dict {LOC AA45 } [get_ports {pcie_rx_n[1]}] ;# GTY_RXN2_103
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set_property -dict {LOC Y41 } [get_ports {pcie_tx_p[1]}] ;# GTY_TXP2_103
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set_property -dict {LOC Y42 } [get_ports {pcie_tx_n[1]}] ;# GTY_TXN2_103
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set_property -dict {LOC Y46 } [get_ports {pcie_rx_p[2]}] ;# GTY_RXP2_103
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set_property -dict {LOC Y47 } [get_ports {pcie_rx_n[2]}] ;# GTY_RXN2_103
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set_property -dict {LOC V41 } [get_ports {pcie_tx_p[2]}] ;# GTY_TXN2_103
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set_property -dict {LOC V42 } [get_ports {pcie_tx_n[2]}] ;# GTY_TXN2_103
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set_property -dict {LOC W44 } [get_ports {pcie_rx_p[3]}] ;# GTY_RXN3_103
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set_property -dict {LOC W45 } [get_ports {pcie_rx_n[3]}] ;# GTY_RXN3_103
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set_property -dict {LOC U43 } [get_ports {pcie_tx_p[3]}] ;# GTY_TXN3_103
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set_property -dict {LOC U44 } [get_ports {pcie_tx_n[3]}] ;# GTY_TXN3_103
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set_property -dict {LOC V46 } [get_ports {pcie_rx_p[4]}] ;# GTY_RXN4_104
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set_property -dict {LOC V47 } [get_ports {pcie_rx_n[4]}] ;# GTY_RXN4_104
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set_property -dict {LOC T41 } [get_ports {pcie_tx_p[4]}] ;# GTY_TXN4_104
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set_property -dict {LOC T42 } [get_ports {pcie_tx_n[4]}] ;# GTY_TXN4_104
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set_property -dict {LOC T46 } [get_ports {pcie_rx_p[5]}] ;# GTY_RXN5_104
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set_property -dict {LOC T47 } [get_ports {pcie_rx_n[5]}] ;# GTY_RXN5_104
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set_property -dict {LOC R43 } [get_ports {pcie_tx_p[5]}] ;# GTY_TXN5_104
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set_property -dict {LOC R44 } [get_ports {pcie_tx_n[5]}] ;# GTY_TXN5_104
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set_property -dict {LOC P46 } [get_ports {pcie_rx_p[6]}] ;# GTY_RXN6_104
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set_property -dict {LOC P47 } [get_ports {pcie_rx_n[6]}] ;# GTY_RXN6_104
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set_property -dict {LOC P41 } [get_ports {pcie_tx_p[6]}] ;# GTY_TXN6_104
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set_property -dict {LOC P42 } [get_ports {pcie_tx_n[6]}] ;# GTY_TXN6_104
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set_property -dict {LOC N44 } [get_ports {pcie_rx_p[7]}] ;# GTY_RXN7_104
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set_property -dict {LOC N45 } [get_ports {pcie_rx_n[7]}] ;# GTY_RXN7_104
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set_property -dict {LOC M41 } [get_ports {pcie_tx_p[7]}] ;# GTY_TXN7_104
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set_property -dict {LOC M42 } [get_ports {pcie_tx_n[7]}] ;# GTY_TXN7_104

‎example/VMK180/fpga/fpga/Makefile‎

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# FPGA settings
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FPGA_PART = xcvm1802-vsva2197-2MP-e-S
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FPGA_TOP = fpga
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FPGA_ARCH = versalprime
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_reset.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/common/example_core_pcie_us.v
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SYN_FILES += rtl/common/example_core_pcie.v
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SYN_FILES += rtl/common/example_core.v
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SYN_FILES += rtl/common/axi_ram.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
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SYN_FILES += lib/pcie/rtl/pcie_msix.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/priority_encoder.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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# IP
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IP_TCL_FILES = ip/versal_cips.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).pdi
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server -url 172.30.0.49:3121 -allow_non_jtag" >> program.tcl
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echo "current_hw_target [get_hw_targets */xilinx_tcf/Xilinx/127.0.0.1:2542]" >> program.tcl
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echo "set_property PARAM.FREQUENCY 10000000 [get_hw_targets */xilinx_tcf/Xilinx/127.0.0.1:2542]" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [get_hw_devices xcvm1802_1]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).pdi} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl

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