A comprehensive collection of reusable HDL IP cores, UVM verification environments, and FPGA synthesis projects, primarily targeting Xilinx Zynq-7000 devices.
hdl/
├── ip/ # Reusable IP cores (RTL library)
├── verification/ # UVM testbenches and verification environments
├── projects/ # FPGA synthesis projects (Vivado)
├── legacy/ # Deprecated Verilog implementations
├── tools/ # Build scripts and utilities
└── docs/ # Documentation
- Xilinx Vivado (tested with version supporting xc7z010clg400-1)
- SystemVerilog compiler (for RTL simulation)
- UVM library (for verification projects)
Navigate to any project directory and run the build script:
cd projects/decoder/vivado
./build.shOr use Vivado TCL directly:
vivado -mode batch -source decoder_project.tclcd verification/tutorial/01_simple_adder/project
vivado -mode batch -source uvm_adder.tclOrganized by functional category:
- axi4_lite_master/ - AXI4-Lite master with LUT support
- axi4_lite_channels/ - Separate read/write channel managers (v2)
- axi4_lite_core/ - Complete AXI4-Lite protocol implementation
- axi4_master/ - Full AXI4 master with read/write managers
- axi4_stream_fifo/ - AXI4-Stream FIFO with backpressure
- skid_buffer/ - Pipeline register with ready/valid handshaking
- dual_port_ram_fifo/ - Dual-port RAM-based FIFO
- float_add/ - Floating-point adder
- decoder/ - Simple combinational decoder
- simple_switch/ - 1-cycle latency packet router
- basic/ - Counters, FSMs, multiplexers, packages
- pmod_vga/ - Complete VGA controller for Pmod VGA display
Each IP component follows the structure:
component_name/
├── src/ # RTL source files
├── sim/ # Testbenches
└── README.md # Component documentation (if available)
UVM-based verification environments:
- tutorial/01_simple_adder/ - Introduction to UVM methodology
- axi4_lite/ - Complete AXI4-Lite protocol verification
- axi4_dma/ - DMA controller verification with custom datatypes
- axi4_stream_fifo/ - AXI4-Stream FIFO verification
- skid_buffer/ - Skid buffer verification
Each verification project contains:
verification_name/
├── dut/ # Design Under Test
├── tb/ # UVM testbench components
└── project/ # Vivado/simulator configuration
Synthesis-ready Vivado projects:
- decoder/ - Simple decoder implementation
- simple_router/ - Packet router with FIFO (includes Xilinx IP)
- axi4_lite/ - AXI4-Lite v1 (legacy Verilog)
- axi4_lite_v2/ - AXI4-Lite v2 (SystemVerilog)
- axi4_lite_master/ - AXI4-Lite master implementation
- skid_buffer/ - Skid buffer with AXI4-Stream VIP integration
- float_add/ - Floating-point adder
- axi4_stream_fifo/ - AXI4-Stream FIFO
Deprecated Verilog implementations kept for reference:
- Original v1 AXI4-Lite components
- Wrapper modules (replaced by SystemVerilog versions)
Additional documentation and guides (see individual files).
- Create directory structure:
ip/category/component_name/{src,sim}/ - Add RTL files to
src/ - Add testbenches to
sim/ - Document interfaces and usage in README.md
- Place TCL script in
projects/component_name/vivado/ - Reference IP using relative paths:
../../../ip/category/component/src/ - Update build script if needed
- Create directory:
verification/component_name/{dut,tb,project}/ - DUT files in
dut/ - UVM components in
tb/ - Vivado/simulation config in
project/
Primary target: Xilinx Zynq-7000 (xc7z010clg400-1)
- Compatible with Zynq UltraScale+ with minor modifications
- Uses Xilinx IP cores (AXI VIP, FIFO Generator)
MIT License - See LICENSE file for details
Contributions welcome! Please:
- Follow existing directory structure
- Use consistent naming (lowercase with underscores)
- Update documentation
- Test builds before committing
Bartosz Rycko