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Add initial JTEC and JTEC+ kernel drafts #3

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147 changes: 147 additions & 0 deletions bootloader-jtec-256K.asm
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; bootloader-jtec-256K.asm
;
; SBECBootloader (https://github.com/dino2gnt/SBECBootloader)
; Copyright (C) 2022, Dino Yancey
;
; MCU: 68HC16Z
; For 256KB Flash chip TMS28F010A 128k+128k or compatible
;
; A feature-rich monolithic kernel for interacting with
; 60HC16Z based Chrysler JTEC (1996-1998) engine management units.
;
ORG $0100
LBRA SETUP ; initialization is at the very end, so it can be run once and overwritten
START: jsr RXBYTE
cmpb #$10 ; cmd 10 will echo 11 (are you alive?)
beq CMD_10
cmpb #$20 ; cmd 20 is bank erase
lbeq CMD_20
cmpb #$30 ; cmd 30 is write flash chunk to mem
lbeq CMD_30
cmpb #$40 ; cmd 40 is read from mem and write to flash
lbeq CMD_40
cmpb #$45 ; cmd 45 is bulk memory dump
lbeq CMD_45
cmpb #$50 ; cmd 50 is read word from EEPROM offset
lbeq CMD_50
cmpb #$55 ; cmd 55 is write word to EEPROM offset
lbeq CMD_55
bne START

CMD_10: ldab #$11
jsr TXBYTE
beq START

TXBYTE:
LDAA $7C0C,Z ; TX function
ANDA #$01
BEQ TXBYTE
STAB $7C0F,Z
LDD #$0043 ; this is the TX delay interval
JSR DELAY
RTS
RXBYTE:
LDAA $7C0D,Z ; RX function
ANDA #$42
CMPA #$40
BNE RXBYTE
LDAB $7C0F,Z
RTS

DELAY:
SUBD #$0001 ; Delay function
BNE DELAY
RTS

RDR_X: NOP ; Reader X byte
; Command 45 / Memory dump:
CMD_45: ldab #$46 ; sequence will be:
; 0x45 0x07 0xFF 0xBF 0x00 0x40 request
; 0x46 0x07 0xFF 0xBF 0x00 0x40 response
; and should return (in this example) 64 bytes from 0x7FFBF to 0x7FFFF
jsr TXBYTE ; TX 0x46 as 0x45 acknowledge
jsr RXBYTE ; RX
tbxk ; RX Byte0 bank / XK e.g. 0x07
jsr TXBYTE ; echo B0
jsr RXBYTE ; RX Byte1 IX high byte, e.g. 0xFF
stab ADRWORD
jsr TXBYTE ; echo B1
jsr RXBYTE ; RX Byte2 IX low , e.g. 0xBF
stab ADRWORD+1
ldx ADRWORD ; X is now XK:FFBF - we go up from here
jsr TXBYTE ; echo B2
jsr RXBYTE ; RX Byte3 counter high byte, e.g. 0x00
stab RDR_X
jsr TXBYTE ; echo B3
jsr RXBYTE ; RX Byte4 counter low byte, e.g. 0x40
stab RDR_X+1
jsr TXBYTE ; echo B4
RDRLOOP: ldab 0,X
jsr TXBYTE ; Echo byte at address X
aix #$01 ; increment the address counter
decw RDR_X
bne RDRLOOP
lbra START
ADRWORD: NOP ; this is the memory word we pull E from

CMD_20: ldab #$21 ; echo 21 for 20 acknowledge
jsr TXBYTE
lbra START ; TODO

CMD_30: ldab #$31 ; request 0x30, 0xFF: upload 255 bytes
jsr TXBYTE ; Send 0x31 acknowledge
lbra START ; TODO

CMD_40: ldab #$41
jsr TXBYTE ; Send 0x41 acknowledge
lbra START ; TODO

; CMD 50 / 55 read & write EEPROM
CMD_50: ldab #$51
jsr TXBYTE ; echo 51
lbra START ; TODO

CMD_55: ldab #$56
jsr TXBYTE ; echo 56
lbra START ; TODO

; SETUP SECTION - everything past this point is overwritten by CMD30 payload
SETUP: orp #$E0 ; set S, MV, H flags in CCR register
ldab #$F ; B = $0F
tbzk ; ZK = B = $F
ldz #$8000 ; Z = $8000
ldab #0 ; B = 0
tbsk ; SK = B = 0
lds #$7F6 ; S = $7F6 = lowest RAM word offset for Stack Pointer
clrb ; B = 0
tbek ; EK = B = 0
tbyk ; YK = B = 0
ldab #4 ; B = 4
tbxk ; XK = B = 4
ldx #$8000 ; XK:IX = $48000
ldd #$148
std SIMCR, Z ; save D to Module Configuration Register
bclr SYPCR, Z, #$80 ; clear SWE flag (software watchdog disabled) in System Protection Control Register
lde #$3130 ; E = value
ste CSOR2, Z ; store E
lde #$5130 ; E = value
ste CSOR1, Z ; store E
lde #$405 ; E = value (flash size = 256 kB)
ste CSBAR2, Z ; store E
ste CSBAR1, Z ; store E
ste CSBAR10, Z ; store E
lde #$6930 ; E = value
ste CSOR10, Z ; store E
ldd #$200 ; D = value
lde #$3070 ; E = value
std CSBAR5, Z ; store E
ste CSOR5, Z ; store E
ldaa #$7C ; A = value
staa PORTQS, Z ; store A
ldaa #$1E ; A = value
staa DDRQS, Z ; store A
ldaa #$1F ; A = value
staa PQSPAR, Z ; store A
ldab #$22 ; bootloader is ready to accept instructions
jsr TXBYTE ; write SCI-bus byte from B (echo)
jmp START ; jump to the command byte reader loop
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