Open
Conversation
lucat1
force-pushed
the
stream-cache
branch
4 times, most recently
from
9679f4e to
d1f56e8
Compare
- wip: implemented stream cache writer, working on reader - implement stream reader - add tests for stream cache - move from stream cache to buffer, change semantics - use a reset state to prevent mem_config_i swallowing in StreamWriter - clarify unit test names - remove old needless edits - tie off other card signals if any
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
These modules allow you to write and (immediately) retrieve data to/from the FPGA's HBM.
The Reader and Writer modules are interconnected with a "link" that notifies the reader of when new data has been fully flushed to the HBM by the writer. This is designed such that a middleware can be placed in between the reader and writer to get the reader to read only parts of the written memory.
Included in this PR is a minor generalization of the StreamWriter and a small bugfix:
mem_config.buffer_readysignal to low when the StreamWriter is resetting, by way of adding a new RESET state to the StreamWriter state machine. This prevents discarding potential databeats while the module is being reset (this can happen, as there are delays added by the reset resync logic).