Skip to content

verilator DUT cpp generation bug #135

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

verilator DUT cpp generation bug #135

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion src/test/scala/verilator/Verilator.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ class VerilatorTest extends FlatSpec with Matchers {
"--compile",
"--genHarness",
"--minimumCompatibility", "3.0.0")
chiselMain(args, () => new doohickey())
chiselMain(args, () => new doohickey(4))
chiselMain(args, () => new doohickey(8))
}
}
6 changes: 4 additions & 2 deletions src/test/scala/verilator/doohickey.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,10 @@ import chisel3._
/**
* The practice of creating Seq's or Vec's of IO's is problematic
*/
class doohickey() extends Module {
val io = IO(new Bundle {})
class doohickey(veclength: Int) extends Module {
val io = IO(new Bundle {
val dummy = Input(Vec(veclength, UInt(4.W)))
})
//TODO: figure out if this idiom is the key point here or if some other example would suffice
val bobs = Seq.fill(16) {
Module(new thingamabob()).io
Expand Down