Final-year Engineering Student passionate about high-performance compute architectures, bridging the gap between digital design and physical implementation.
- Active Project: Exploring ASICs
- Core Expertise: RTL Design and Verification, CMOS basics
- Domains: Digital/Physical Design, DFT, High-Performance Compute Architectures, AI Hardware Acceleration, CPU/GPU Microarchitecture
- Hardware Description: Verilog, SystemVerilog
- Physical Design: Cadence (Virtuoso, Genus, Innovus), Synopsys (Design Compiler, iCC2), OpenRAM
- DFT & MBSIT Cadence(Modus, Conformal), Mentor Graphics(Tessent shell)
- Simulation: ModelSim, QuestaSim, GTKWAVE
- TinyGPU — Minimal GPU Core in SystemVerilog
- MBIST & BIRA Implementation — Using Siemens Tessent
- DDR3 Memory Controller Interface — With FPGA
- Bitcoin miner — With FPGA
- 1×3 Router Design & Verification — In Verilog