Skip to content

@SkillSurf SkillSurf

Change the repository type filter

All

    Repositories list

    20 repositories

    • frac-n-pll-vco-smacd_2026

      Public
      A 2.4GHz Type-II ∆Σ Fractional-N Phase Locked Loop (PLL) with a Type IV Cross-Coupled Differential LC Voltage-Controlled Oscillator (VCO) for Wifi/Bluetooth App…
      Jupyter Notebook
      •0•3•10•0•Updated Apr 15, 2026Apr 15, 2026

    • soc_mac

      Public
      0•0•0•0•Updated Apr 13, 2026Apr 13, 2026

    • os-ina-pso-smacd_2026

      Public
      Design of an Area Optimized Low-Power Low-Noise CMOS Instrumentation Amplifier in SKY130 using Hybrid Particle Swarm Optimization
      Jupyter Notebook
      •
      MIT License
      •0•2•0•0•Updated Apr 8, 2026Apr 8, 2026

    • .github

      Public
      0•0•0•0•Updated Apr 7, 2026Apr 7, 2026

    • systemverilog

      Public
      SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
      Tcl
      •
      MIT License
      •17•55•0•0•Updated Feb 27, 2026Feb 27, 2026

    • art_of_aicd

      Public
      The Art of Analog IC Design Free One Day Workshop organized by SkillSurf.
      HTML
      •
      MIT License
      •1•0•0•1•Updated Jan 26, 2026Jan 26, 2026

    • intro_comparch

      Public
      Hands-on Introduction to Computer Architecture with RISC‑V
      SystemVerilog
      •0•0•0•0•Updated Nov 17, 2025Nov 17, 2025

    • ttsky25_se_opamp

      Public
      Template for Operational Amplifier Design submission for Tiny Tapeout SKY130 (ChipFoundry) shuttles
      Verilog
      •
      Apache License 2.0
      •0•3•0•0•Updated Nov 12, 2025Nov 12, 2025

    • ttsky25_se_opamps

      Public
      TTSKY25b Low-power Single-ended Op-Amp tapeout from AICD Contest
      Verilog
      •
      Apache License 2.0
      •0•2•0•0•Updated Nov 10, 2025Nov 10, 2025

    • cmos-pll-ihp-sg13g2

      Public
      A charge-pump (CP) based Phase Locked Loop (PLL) using IHP SG13G2 130nm technology.
      Jupyter Notebook
      •
      MIT License
      •0•3•0•0•Updated Sep 1, 2025Sep 1, 2025

    • sg13g2_asic_flow

      Public
      SG13G2 ASIC flow design template
      Python
      •8•1•0•0•Updated Apr 9, 2025Apr 9, 2025

    • 8b-sar-adc-unic_cass

      Public
      100KSPS 8-bit Fully-differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) for Low-power Applications (UNIC-CASS program by IEEE…
      Verilog
      •
      Apache License 2.0
      •5•2•0•0•Updated Nov 24, 2024Nov 24, 2024

    • tt09-matmul-system

      Public
      Matmul + UART + AXI Stream
      Verilog
      •
      Apache License 2.0
      •2•1•0•0•Updated Nov 7, 2024Nov 7, 2024

    • tinytapout-matmul-system

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Nov 7, 2024Nov 7, 2024

    • cmos_inverter_sky130

      Public
      CMOS Inverter Design, Analysis and Layout in SKY130
      MIT License
      •5•3•0•0•Updated Sep 21, 2024Sep 21, 2024

    • ML4_edgeAI

      Public
      C
      •2•0•0•0•Updated Sep 1, 2024Sep 1, 2024

    • introduction_qc

      Public
      Introduction to Quantum Computing Free One-Day Workshop
      Mathematica
      •
      MIT License
      •1•4•0•0•Updated Jun 9, 2024Jun 9, 2024

    • modern_cpp

      Public
      C++
      •
      MIT License
      •0•0•0•0•Updated Jun 9, 2024Jun 9, 2024

    • introduction_genAI

      Public
      Introduction to GenAI Free One-Day Workshop
      Jupyter Notebook
      •
      MIT License
      •3•20•0•0•Updated Jun 9, 2024Jun 9, 2024

    • a-risc

      Public
      A Custom RISC CPU in 99 Lines of SystemVerilog
      SystemVerilog
      •1•4•0•0•Updated Jan 19, 2023Jan 19, 2023
    ProTip! When viewing an organization's repositories, you can use the props. filter to filter by custom property.