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refine io emulation#8864

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lifeix wants to merge 4 commits intoprojectacrn:multi-arch-devfrom
lifeix:io_req
Open

refine io emulation#8864
lifeix wants to merge 4 commits intoprojectacrn:multi-arch-devfrom
lifeix:io_req

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@lifeix lifeix commented Apr 28, 2026

This patchset tries to common io emulation for PIO/MMIO.

However, this patchset doesn't emable mmio vuart for risc-v since virtual PLIC doesn't enabled.

Fei Li (4):
io_req: use bitmap to record free mmio node
io_req: try to common io req for pio and mmio
io_req: enable io_req for risc-v
enable HSM

Signed-off-by: Fei Li fei1.li@intel.com
Acked-by: Wang Yu1 yu1.wang@intel.com

lifeix added 4 commits April 28, 2026 20:00
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
For PIO and MMIO io request, the register and handler logic is almost the same.
This patch tries to common the io req for PIO and MMIO by:
1) use the same lock, io_bitmap and io_node to maintain/protect PIO/MMIO request
2) common the io_node allocate, PIO/MMIO register and handler code

This patch also touch some logic changes:
1) For PIO request, use a private_data to pass parameter for PIO request handler
like MMIO request. Now the IO handler prototype is like
int32_t io_handler(struct io_request *io_req, void *private_data);
So the vCPU paramater is removed.
2) For guest pm and reset PIO request, since the vCPU paramater is removed, so use
the vBSP to do the S3/S5 and reset for guest VM.

Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
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2 participants