Skip to content

UefiPayloadPkg,MdeModulePkg,MdePkg: Add PCIe capability structures for DPC and DLF, remove MR-IOV #11579

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: master
Choose a base branch
from
+190 −105
Open

UefiPayloadPkg,MdeModulePkg,MdePkg: Add PCIe capability structures for DPC and DLF, remove MR-IOV #11579

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
d28f1f7
UefiPayloadPkg: Remove PcdMrIovSupport - deprecated in PCIe 6.0
jkolakow Nov 13, 2025
0920ae8
MdeModulePkg: Remove PcdMrIovSupport - deprecated in PCIe 6.0
jkolakow Nov 13, 2025
b855c42
MdePkg: Add PCIe capability structures for DPC and DLF
jkolakow Nov 13, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 0 additions & 2 deletions MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@ typedef struct _PCI_BAR PCI_BAR;

#define EFI_PCI_IOV_POLICY_ARI 0x0001
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004

typedef enum {
PciBarTypeUnknown = 0,
Expand Down Expand Up @@ -269,7 +268,6 @@ struct _PCI_IO_DEVICE {
UINT8 PciExpressCapabilityOffset;
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
PCI_BAR VfPciBar[PCI_MAX_BAR];
UINT32 SystemPageSize;
UINT16 InitialVFs;
Expand Down
1 change: 0 additions & 1 deletion MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUMES

Expand Down
12 changes: 0 additions & 12 deletions MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2460,18 +2460,6 @@ CreatePciIoDevice (
}
}

if (PcdGetBool (PcdMrIovSupport)) {
Status = LocatePciExpressCapabilityRegBlock (
PciIoDevice,
EFI_PCIE_CAPABILITY_ID_MRIOV,
&PciIoDevice->MrIovCapabilityOffset,
NULL
);
if (!EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
}
}

PciIoDevice->ResizableBarOffset = 0;
if (PcdGetBool (PcdPcieResizableBarSupport)) {
Status = LocatePciExpressCapabilityRegBlock (
Expand Down
6 changes: 0 additions & 6 deletions MdeModulePkg/MdeModulePkg.dec
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2045,12 +2045,6 @@
# @Prompt Enable ARI support.
gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE|BOOLEAN|0x10000045

## Indicates if the Multi Root I/O virtualization is supported.<BR><BR>
# TRUE - Multi Root I/O virtualization is supported.<BR>
# FALSE - Multi Root I/O virtualization is not supported.<BR>
# @Prompt Enable MRIOV support.
gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE|BOOLEAN|0x10000046

## Single root I/O virtualization virtual function memory BAR alignment.<BR><BR>
# BITN set indicates 2 of n+12 power<BR>
# BIT0 set indicates 4KB alignment<BR>
Expand Down
6 changes: 0 additions & 6 deletions MdeModulePkg/MdeModulePkg.uni
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -560,12 +560,6 @@
"TRUE - Alternative Routing-ID is supported.<BR>\n"
"FALSE - Alternative Routing-ID is not supported.<BR>"

#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdMrIovSupport_PROMPT #language en-US "Enable MRIOV support"

#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdMrIovSupport_HELP #language en-US "Indicates if the Multi Root I/O virtualization is supported.<BR><BR>\n"
"TRUE - Multi Root I/O virtualization is supported.<BR>\n"
"FALSE - Multi Root I/O virtualization is not supported.<BR>"

#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSrIovSystemPageSize_PROMPT #language en-US "SRIOV system page size"

#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSrIovSystemPageSize_HELP #language en-US "Single root I/O virtualization virtual function memory BAR alignment.<BR><BR>\n"
Expand Down
8 changes: 5 additions & 3 deletions MdePkg/Include/IndustryStandard/Pci30.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,9 +39,11 @@
**/
#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)

///
/// PCI Capability List IDs and records
///
//
// Symbol EFI_PCI_CAPABILITY_ID_PCIEXP is obsolete, use PCI_EXPRESS_CAPABILITY_ID.
// PCI_EXPRESS_CAPABILITY_ID is defined beside the capability registers structure
// in PciExpress21.h. This ID is not EFI nor PCI symbol, but PCI Express.
//
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10

#pragma pack(1)
Expand Down
83 changes: 47 additions & 36 deletions MdePkg/Include/IndustryStandard/PciExpress21.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,17 @@
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

#pragma pack(1)
///
/// PCI Express Capability Structure
///

//
// PCI Express Capability Structure version 2.
// Mandatory for PCI Express devices. If not present it is not PCI Express device, thus no extended config space.
// Version 1 ends at PCI_CAPABILITY_PCIEXP::RootStatus register.
// Version 2 extends version 1 up to PCI_CAPABILITY_PCIEXP::SlotStatus2 register.
//
#define PCI_EXPRESS_CAPABILITY_ID 0x0010
#define PCI_EXPRESS_CAPABILITY_VER1 0x1
#define PCI_EXPRESS_CAPABILITY_VER2 0x2

typedef union {
struct {
UINT16 Version : 4;
Expand Down Expand Up @@ -397,29 +405,29 @@ typedef union {
} PCI_REG_PCIE_SLOT_CAPABILITY2;

typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
PCI_REG_PCIE_LINK_CONTROL LinkControl;
PCI_REG_PCIE_LINK_STATUS LinkStatus;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
PCI_REG_PCIE_ROOT_CONTROL RootControl;
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
PCI_REG_PCIE_ROOT_STATUS RootStatus;
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
UINT16 DeviceStatus2;
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
EFI_PCI_CAPABILITY_HDR Hdr; // Offset 00 size 2
PCI_REG_PCIE_CAPABILITY Capability; // Offset 02 size 2
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; // Offset 04 size 4
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; // Offset 08 size 2
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; // Offset 0A size 2
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; // Offset 0C size 4
PCI_REG_PCIE_LINK_CONTROL LinkControl; // Offset 10 size 2
PCI_REG_PCIE_LINK_STATUS LinkStatus; // Offset 12 size 2
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; // Offset 14 size 4
PCI_REG_PCIE_SLOT_CONTROL SlotControl; // Offset 18 size 2
PCI_REG_PCIE_SLOT_STATUS SlotStatus; // Offset 1A size 2
PCI_REG_PCIE_ROOT_CONTROL RootControl; // Offset 1C size 2
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; // Offset 1E size 2
PCI_REG_PCIE_ROOT_STATUS RootStatus; // Offset 20 size 4 - Ver1 ends here
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; // Offset 24 size 4
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; // Offset 28 size 2
UINT16 DeviceStatus2; // Offset 2A size 2
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; // Offset 2C size 4
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; // Offset 30 size 2
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; // Offset 32 size 2
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2; // Offset 34 size 4
UINT16 SlotControl2; // Offset 38 size 2
UINT16 SlotStatus2; // Offset 3A size 2
} PCI_CAPABILITY_PCIEXP;

#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
Expand All @@ -430,13 +438,18 @@ typedef struct {
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20

//
// for SR-IOV
// Definitions EFI_PCIE_CAPABILITY_ID_ARI, EFI_PCIE_CAPABILITY_ID_ATS, EFI_PCIE_CAPABILITY_ID_SRIOV,
// are obsolete, will be removed in future. Instead use PCI Express definitions
// PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID, PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID,
// PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID.
//
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
#define EFI_PCIE_CAPABILITY_ID_ARI PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
#define EFI_PCIE_CAPABILITY_ID_ATS PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID
#define EFI_PCIE_CAPABILITY_ID_SRIOV PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID

//
// Single Root IO Virtualization (SR-IOV) Extended Capability Structure.
//
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID 0x0010
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_VER1 0x1

Expand Down Expand Up @@ -740,10 +753,9 @@ typedef struct {

#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)

/// Address Translation Services Extended Capability Structure
///
/// Based on section 5.1 of PCI Express Address Translation Services Specification 1.1
///@{
//
// Address Translation Services (ATS) Extended Capability Structure.
//
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID 0x000F
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_VER1 0x1

Expand Down Expand Up @@ -771,7 +783,6 @@ typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY Capability;
PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL Control;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS;
///@}

#pragma pack()

Expand Down
98 changes: 83 additions & 15 deletions MdePkg/Include/IndustryStandard/PciExpress31.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,74 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

#pragma pack(1)

//
// Downstream Port Containment (DPC) Extended Capability.
//
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DPC_ID 0x001D

typedef union {
struct {
UINT16 DpcInterruptMsgNo : 5; // [4:0]
UINT16 RpExtensionsForDpc : 1; // [5]
UINT16 PoisonedTlpEgressBlockingSupp : 1; // [6]
UINT16 DpcSoftwareTriggerSupp : 1; // [7]
UINT16 RpPioLogSize : 4; // [11:8] Bits [3:0] of log size
UINT16 DlActiveErrCorSignalingSupp : 1; // [12]
UINT16 RpPioLogSizeExt : 1; // [13] Bit [4] of log size
UINT16 Reserved : 2; // [15:14]
} Bits;
UINT32 Uint16;
} PCI_EXPRESS_REG_DPC_CAPABILITY;

typedef union {
struct {
UINT16 DpcTriggerEn : 2; // [1:0]
UINT16 DpcCompletionCtl : 1; // [2]
UINT16 DpcInterruptEn : 1; // [3]
UINT16 DpcErrCorEn : 1; // [4]
UINT16 PoisonedTlpEgressBlockingEn : 1; // [5]
UINT16 DpcSoftwareTrigger : 1; // [6]
UINT16 DlActiveErrCorEn : 1; // [7]
UINT16 DpcSigSfwEn : 1; // [8]
UINT16 Reserved : 7; // [15:9]
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_REG_DPC_CONTROL;

typedef union {
struct {
UINT16 DpcTriggerStatus : 1; // [0]
UINT16 DpcTriggerReason : 2; // [2:1]
UINT16 DpcInterruptStatus : 1; // [3]
UINT16 DpcRpBusy : 1; // [4]
UINT16 DpcTriggerReasonExtension : 2; // [6:5]
UINT16 Reserved0 : 1; // [7]
UINT16 RpPioFirstErrorPointer : 5; // [12:8]
UINT16 DpcSigSfwStatus : 1; // [13]
UINT16 Reserved1 : 2; // [15:14]
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_REG_DPC_STATUS;

typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_DPC_CAPABILITY Capability; // Offset 04h size 2
PCI_EXPRESS_REG_DPC_CONTROL Control; // Offset 06h size 2
PCI_EXPRESS_REG_DPC_STATUS Status; // Offset 08h size 2
UINT16 ErrSourceId; // Offset 0Ah size 2
UINT32 RpPioStatus; // Offset 0Ch size 4
UINT32 RpPioMask; // Offset 10h size 4
UINT32 RpPioSeverity; // Offset 14h size 4
UINT32 RpPioSysErr; // Offset 18h size 4
UINT32 RpPioException; // Offset 1Ch size 4
UINT32 RpPioHdrLog[4]; // Offset 20h size 16 header log DW 1-4
UINT32 RpPioImpSpecLog; // Offset 30h size 4
UINT32 RpPioHdrLogExt[10]; // Offset 34h size 40 header log DW 5-14
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DPC;

//
// L1 PM Substates Extended Capability.
//
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1

Expand Down Expand Up @@ -67,31 +135,32 @@ typedef struct {
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;

/// Process Address Space ID Extended Capability Structure
///
/// Based on section 7.29 of PCI Express Base Specification 3.1
///@{
//
// Process Address Space ID (PASID) Extended Capability Structure.
//
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1

typedef union {
struct {
UINT16 PasidSupport : 1;
UINT16 ExecutePermissionSupport : 1;
UINT16 PrivilegedModeSupport : 1;
UINT16 Reserved1 : 5;
UINT16 MaxPasidWidth : 5;
UINT16 Reserved2 : 3;
UINT16 Reserved0 : 1; // [0]
UINT16 ExecutePermissionSupport : 1; // [1]
UINT16 PrivilegedModeSupport : 1; // [2]
UINT16 TranslatedReqWithPasidSupport : 1; // [3]
UINT16 Reserved1 : 4; // [7:4]
UINT16 MaxPasidWidth : 5; // [12:8]
UINT16 Reserved2 : 3; // [15:13]
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY;

typedef union {
struct {
UINT16 PasidEnable : 1;
UINT16 ExecutePermissionEnable : 1;
UINT16 PrivilegedModeEnable : 1;
UINT16 Reserved : 13;
UINT16 PasidEnable : 1; // [0]
UINT16 ExecutePermissionEnable : 1; // [1]
UINT16 PrivilegedModeEnable : 1; // [2]
UINT16 TranslatedReqWithPasidEnable : 1; // [3]
UINT16 Reserved : 12;
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL;
Expand All @@ -101,7 +170,6 @@ typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability;
PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID;
///@}

#pragma pack()

Expand Down
Loading
Loading