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The current handling of non-coherent DMA is very inefficient:

  • outbound DMA uses bounce buffers unnecessarily, considering that a bus master read cannot break coherency, and can therefore access the host buffer directly without the risk of data corruption;

  • bounce buffers are allocated from uncached memory, resulting in slow CopyMem() performance, and unnecessary overhead in allocating, remapping and freeing the pages, which also involves EFI memory map changes each time.

So refactor the logic, and tweak it so that:

  • Bounce buffering is only performed when the host buffer is out of DMA range for the device, or when performing misaligned inbound DMA on a host buffer that is mapped cacheable;

  • Cache maintenance is only performed when the buffer presented to the device is mapped cacheable.

  • Bounce buffers are pool allocated, which is much more efficient and does not involve EFI memory map changes in the common case.

The current handling of non-coherent DMA is very inefficient:

- outbound DMA uses bounce buffers unnecessarily, considering that a bus
  master read cannot break coherency, and can therefore access the host
  buffer directly without the risk of data corruption;

- bounce buffers are allocated from uncached memory, resulting in slow
  CopyMem() performance, and unnecessary overhead in allocating,
  remapping and freeing the pages, which also involves EFI memory map
  changes each time.

So refactor the logic, and tweak it so that:

- Bounce buffering is only performed when the host buffer is out of DMA
  range for the device, or when performing misaligned inbound DMA on a
  host buffer that is mapped cacheable;

- Cache maintenance is only performed when the buffer presented to the
  device is mapped cacheable.

- Bounce buffers are pool allocated, which is much more efficient and
  does not involve EFI memory map changes in the common case.

Signed-off-by: Ard Biesheuvel <[email protected]>
@ardbiesheuvel
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@eeshanl

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2 participants