[Verif] Always add clock trigger to HasBeenReset process (#9212)

Always add a `posedge clock` trigger to the always process created for
`verif.has_been_reset` operations, even if the reset is asynchronous.
Until now we would emit an `always @(posedge reset)` process, which some
EDA tools do not process properly. With this commit, we produce
`always @(posedge clock, posedge reset)` for asynchronous HBR ops, and
`always @(posedge clock)` for synchronous HBR ops.

Author: fabianschuiki

lib/Conversion/VerifToSV/VerifToSV.cpp

@@ -100,17 +100,17 @@ struct HasBeenResetConversion : public OpConversionPattern<HasBeenResetOp> {
     // Create the `always` block that sets the register to 1 as soon as the
     // reset is initiated. For async resets this happens at the reset's posedge;
     // for sync resets this happens on the clock's posedge if the reset is set.
-    Value triggerOn = op.getAsync() ? reset : clock;
-    sv::AlwaysOp::create(
-        rewriter, op.getLoc(), sv::EventControl::AtPosEdge, triggerOn, [&] {
-          auto assignOne = [&] {
-            sv::PAssignOp::create(rewriter, op.getLoc(), reg, constOne);
-          };
-          if (op.getAsync())
-            assignOne();
-          else
-            sv::IfOp::create(rewriter, op.getLoc(), reset, assignOne);
-        });
+    SmallVector<sv::EventControl, 2> eventControl{sv::EventControl::AtPosEdge};
+    SmallVector<Value, 2> triggerOn{clock};
+    if (op.getAsync()) {
+      eventControl.push_back(sv::EventControl::AtPosEdge);
+      triggerOn.push_back(reset);
+    }
+    sv::AlwaysOp::create(rewriter, op.getLoc(), eventControl, triggerOn, [&] {
+      sv::IfOp::create(rewriter, op.getLoc(), reset, [&] {
+        sv::PAssignOp::create(rewriter, op.getLoc(), reg, constOne);
+      });
+    });
 
     // Derive the actual result value:
     //   hasBeenReset = (hasBeenResetReg === 1) && (reset === 0);

test/Conversion/VerifToSV/verif-to-sv.mlir

@@ -15,8 +15,10 @@ hw.module @HasBeenResetAsync(in %clock: i1, in %reset: i1, out out: i1) {
   // CHECK-NEXT:   }
   // CHECK-NEXT: }
 
-  // CHECK-NEXT: sv.always posedge %reset {
-  // CHECK-NEXT:   sv.passign %hasBeenResetReg, %true : i1
+  // CHECK-NEXT: sv.always posedge %clock, posedge %reset {
+  // CHECK-NEXT:   sv.if %reset {
+  // CHECK-NEXT:     sv.passign %hasBeenResetReg, %true : i1
+  // CHECK-NEXT:   }
   // CHECK-NEXT: }
 
   // CHECK-NEXT: [[REG:%.+]] = sv.read_inout %hasBeenResetReg