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Pull requests: llvm/circt

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Pull requests list

[ImportVerilog][NFC] Swap primitive tests to use wires
#10257 opened Apr 17, 2026 by TaoBi22 Contributor Loading…
1
[ImportVerilog] Fix hierarchical name resolution across deduped module instances
#10255 opened Apr 17, 2026 by jpienaar Member Loading…
[PyRTG] Simplify instruction calls RTG Involving the `rtg` dialect
#10252 opened Apr 17, 2026 by maerhart Member Loading…
3
[LowerToHW] Avoid "assert/assume/cover" string comparison, refactor label creation, NFC
#10251 opened Apr 17, 2026 by uenoku Member Loading…
[CellIFT] Add CellIFT instrumentation pass for HW/Comb/Seq IR
#10250 opened Apr 17, 2026 by flaviens Loading…
8
[ESI][PyCDE] OneItemBufferFromHost channel DMA: Fix buffer issue ESI PyCDE Python CIRCT Design Entry API
#10247 opened Apr 17, 2026 by teqdruid Contributor • Draft
4
[Synth] Make LowerVariadic run on any operation.
#10242 opened Apr 16, 2026 by joaovam Contributor Loading…
1
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
6
Add union roundtrip
#10236 opened Apr 16, 2026 by jpienaar Member Loading…
1
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
[FIRRTL][LowerLayers] Add probe type support
#10223 opened Apr 15, 2026 by prithayan Contributor Loading…
1
[Sim] Add cascade erase for print/proc.print format/get_file producer chains
#10204 opened Apr 14, 2026 by nanjo712 Contributor Loading…
4
[FIRRTL] InferDomains: drive undriven domain wires
#10197 opened Apr 13, 2026 by rwy7 Contributor Loading…
2
[Synth][CutRewriter] Add timing-preserving area-flow reselection
#10193 opened Apr 13, 2026 by uenoku Member • Draft
5
[SSP] Reimplement auxiliary dependences without symbols
#10189 opened Apr 12, 2026 by jopperm Contributor Loading…
1
don't emit redundant write_en = 0 for seq_mem
#10174 opened Apr 10, 2026 by Abhilekhgautam Loading…
1
2
DRAFT: [3/2] [Moore] Lower class object access and virtual dispatch through LLVM memory
#10166 opened Apr 9, 2026 by Scheremo Contributor • Draft
[Moore][ImportVerilog] Implement static $cast via materializeConversion ImportVerilog
#10156 opened Apr 8, 2026 by sunhailong2001 Contributor Loading…
14
[FIRRTLToHW] Lower FIRRTL prints to Sim
#10153 opened Apr 8, 2026 by nanjo712 Contributor Loading…
2
[FIRRTLToHW] Lower firrtl.attach to new hw.attach and migrate SV-specific lowering logic to HWToSV.
#10138 opened Apr 6, 2026 by nanjo712 Contributor Loading…
6
[FIRRTL] Fix getBitWidth to handle AnalogType
#10136 opened Apr 6, 2026 by unlsycn Member Loading…
[2/2] [MooreToCore] Lower vtable method loads and vptr init
#10130 opened Apr 5, 2026 by Scheremo Contributor • Draft
1
[1/2] [MooreToCore] Lower symbolic vtables to LLVM globals
#10129 opened Apr 5, 2026 by Scheremo Contributor • Draft
10
[Verif] Preserve labeled assert/assume ops during canonicalization verif
#10114 opened Apr 3, 2026 by fabianschuiki Contributor Loading…
3
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